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9DB1933 Datasheet(PDF) 13 Page - Renesas Technology Corp |
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9DB1933 Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 18 page ![]() IDT® Nineteen Output Differential Buffer for PCIe Gen3 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 13 1676A—07/12/10 SMBusTable: Reserved Register Pin # Name Control Function Type 0 1 Default Bit 7 R 1 Bit 6 R 1 Bit 5 R 1 Bit 4 R 1 Bit 3 R 1 Bit 2 R 0 Bit 1 R 1 Bit 0 R 1 SMBusTable: Output Control Register Pin # Name Control Function Type 0 1 Default Bit 7 DIF_7 Output Control RW Hi-Z Enable 1 Bit 6 DIF_6 Output Control RW Hi-Z Enable 1 Bit 5 DIF_5 Output Control RW Hi-Z Enable 1 Bit 4 DIF_4 Output Control RW Hi-Z Enable 1 Bit 3 DIF_3 Output Control RW Hi-Z Enable 1 Bit 2 DIF_2 Output Control RW Hi-Z Enable 1 Bit 1 DIF_1 Output Control RW Hi-Z Enable 1 Bit 0 DIF_0 Output Control RW Hi-Z Enable 1 SMBusTable: Output and PLL BW Control Register Pin # Name Control Function Type 0 1 Default Bit 7 RW High BW Low BW 1 Bit 6 RW Bypass PLL 1 Bit 5 DIF_13 Output Control RW Hi-Z Enable 1 Bit 4 DIF_12 Output Control RW Hi-Z Enable 1 Bit 3 DIF_11 Output Control RW Hi-Z Enable 1 Bit 2 DIF_10 Output Control RW Hi-Z Enable 1 Bit 1 DIF_9 Output Control RW Hi-Z Enable 1 Bit 0 DIF_8 Output Control RW Hi-Z Enable 1 Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Pin # Name Control Function Type 0 1 Default Bit 7 R X Bit 6 R X Bit 5 R X Bit 4 R X Bit 3 R X Bit 2 R X Bit 1 R X Bit 0 R X 72 see note PLL_BW# adjust see note BYPASS# test mode / PLL Byte 3 8 Byte 1 - - - - Byte 0 - - Reserved - - Reserved Reserved Readback Readback - OE9# Input Readback - OE8# Input Readback Readback Readback - OE7# Input Readback Readback - OE_01234# Input Readback Readback - OE5# Input Readback - OE6# Input Readback Byte 2 Reserved Readback - SMB_A2_PLLBYP# In Readback Readback - HIGH_BW# In Readback Reserved Reserved Reserved Reserved |
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