VSC8541-01 datasheet(49/100 Pages) MICROSEMI

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Registers

VMDS-10496 VSC8541-01 Datasheet Revision 4.2

4.2.18

Error Counter 2

The bits in register 20 provide an error counter. The following table shows the settings available.

4.2.19

Error Counter 3

The bits in register 21 provide an error counter. The following table shows the settings available.

4.2.20

Extended Control and Status

The bits in register 22 provide additional device control and readouts. The following table shows the

settings available.

Table 39 •

Extended Control and Status, Address 20 (0x14)

Bit

Name

Access Description

Default

15:8 Reserved

Reserved.

7:0

100/1000 false carrier counter RO

8-bit counter that saturates when it reaches 255.

These bits are self-clearing when read.

0x00

Table 40 •

Extended Control and Status, Address 21 (0x15)

Bit

Name

Access Description

Default

15:8 Reserved

Reserved.

7:0

Copper media link disconnect counter RO

8-bit counter that saturates when it reaches 255.

These bits are self-clearing when read.

0x00

Table 41 •

Extended Control and Status, Address 22 (0x16)

Bit

Name

Access Description

Default

Force 10BASE-T link high

R/W

Sticky bit.

1: Bypass link integrity test.

0: Enable link integrity test.

Jabber detect disable

R/W

Sticky bit.

1: Disable jabber detect.

Disable 10BASE-T echo

R/W

Sticky bit.

1: Disable 10BASE-T echo.

Disable SQE mode

R/W

Sticky bit.

1: Disable SQE mode.

11:10

10BASE-T squelch control

R/W

Sticky bit.

00: Normal squelch.

01: Low squelch.

10: High squelch.

11: Reserved.

Sticky reset enable

R/W

Super-sticky bit.

1: Enabled.

EOF Error

This bit is self-clearing.

1: EOF error detected.

10BASE-T disconnect state RO

This bit is self-clearing.

1: 10BASE-T link disconnect detected.

10BASE-T link status

1: 10BASE-T link active.

5:1

Reserved

Reserved.

VSC8541-01 Datasheet(PDF) 49 Page - Microsemi Corporation

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