Data Sheet

ZL40293

ZL40293

March 2019

© 2019 Microsemi Corporation

21

PCIe Electrical Characteristics

PCIe measurement are related only to ZL40293 device. Test setup is shown Figure 20.

Table 17

PCIe Electrical Characteristics

Parameter

Sym.

Min.

Typ.

Max.

Units

Notes

1

Rising edge rate

Rise_rate

1.4

1.6

2

V/ns

(2), (3)

2

Falling edge rate

Fall_rate

1.4

1.6

2

V/ns

(2), (3)

3

Differential High Voltage

VIH

0.7

V

(2)

4

Differential Low Voltage

VIL

-0.7

V

(2)

5

Single ended high voltage

VSIH

0.7

0.76

0.82`

V

DC Measurement

6

Single ended low voltage

VSIL

-0.05

0

0.05

V

DC Measurement

7

Absolute Crossing Voltage

VCROSS

0.275

0.35

V

(1), (4), (5)

8

Variation of VCROSS over all rising clock edges

∆VCROSS

0.08

V

(1), (4), (9)

9

Ring back voltage margin

VRB

-0.3

-0.3

V

(2), (11)

10

Time before VRB is allowed

tSTABLE

500

(2), (11)

11

Average Clock Period Accuracy

TPERIOD_AVG

NA

NA

ppm

(10)

12

Absolute Period

TPERIOD_ABS

NA

NA

ns

(6)

13

Cycle-to-cycle jitter

TJCC

3.5

6

ps

peak to

peak

(2)

14

Absolute Maximum voltage

VMAX

0.8

V

(1), (7)

15

Absolute Minimum voltage

VMIN

-0.3

V

(1), (8)

16

Output Duty-Cycle (when input has 50% duty-cycle)

Duty_cycle

49

50

51

%

(2)

17

Rising to falling edge matching

r/f match

6

%

(1), (7)

18

Clock Source DC impedance (CK)

ZC-DC_CK

50 - 5%

50

50 + 5%

Ω

DC Measurement

19

Clock Source DC impedance (CK#)

ZC-DC_CK#

50

– 5%

50

50 + 5%

Ω

DC Measurement

20

Output frequency

FMAX

0

250

MHz

21

Output to output skew

tOOSK

50

ps

22

Device to device output skew

tDOOSK

0.5

ns

23

Input to output delay

tIOD

0.9

1.5

ns

24

Output enable time

tEN

10

cycles

25

Output disable time

tDIS

10

cycles

* Values are over Recommended Operating Conditions

(0)

Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets

(1)

Measurement taken from single ended waveform

(2)

Measurement taken from differential waveform.

(3)

Measured from -150 mV to +150 mV on the differential waveform (derived from CK minus CK#) The signal must be monotonic through the

measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. See Figure 18

(4)

Measured at crossing point where the instantaneous voltage value of the rising edge of CK equals the falling edge of CK# . See Figure 15

(5)

Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this

measurement. See Figure 15.

(6)

This requirement, from PCI Express Base Specification, Revision 4.0 is applicable only to clock generators and not to buffers. A clock buffer is a transparent

device whose output clock period follows the input clock period.

(7)

Defined as the maximum instantaneous voltage including overshoot. See Figure 15.

(8)

Defined as the minimum instantaneous voltage including undershoot. See Figure 15.

(9)

Defined as the total variation of all crossing voltages of Rising CK and Falling CK# This is the maximum allowed variance in VCROSS for any particular

system. See Figure 16.

(10) The PPM requirement from PCIe Express Base Specification, Revision 4.0 is related to clock generation devices. This requirement is not applicable to buffers

because buffer’s output frequency accuracy is identical to the frequency accuracy of the source driving the buffer.

(11) TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after20 rising/falling edges before it is allowed to droop

back into the VRB ±100 mV differential range. See Figure 19.

(12) Matching applies to rising edge rate for CKx and falling edge rate for CK#x. It is measured using a ±75 mV window centered on the median cross point where

CKx rising meets CK#x falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The

Rise Edge Rate of CKx should be compared to the Fall Edge Rate of CK#x the maximum allowed difference should not exceed 20% of the slowest edge rate.

See Figure 17.