STPM066S datasheet(27/67 Pages) STMICROELECTRONICS

27 / 67 page

Table 10. Input CLK, DI

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

Vin L

Input low level

–

Vin H

Input high level

–

2.3

–

Vin Hyst Input hysteresis

–

0.2

0.4

–

I in

Pull down current at input

Vin = 1.5 V

6.5

µ A

Cin

Input capacitance at input pins CSN, CLK, DI

Guaranteed by design

–

fCLK

SPI input frequency at CLK

Writing / for Reading see note below.

–

MHz

Application note:

The setup and hold timings of the SPI Master have to be considered when selecting the maximum SPI CLK

frequency. While the DI signal can switch up to 1 MHz, the DO pin is connected to an open drain structure,

therefore the Rise and Fall times of the DO signal need to be calculated as a function of the Pull up resistor

(RDO_PullUp), the capacitive load (CDO_load) and the input High Level and input Low Level thresholds of the SPI

Master (see Figure 17).

Figure 17. SPI Master

Ideal switch

RDO_PullUp

VPullUp_Supply

RDO_switch

CDO_load

Microcontroller - SPI Master

PMIC - SPI Slave

The capacitive load is the sum of all the capacitance seen at DO pin, including PCB traces and other ICs. Rise

time is given by equation Eq. (8), fall time by equation Eq. (9) (hypothesis of RDO_Pullup >> RDO_Switch).

tDO.rise=−CDO.load*RDO.PullUp*ln1−Vin.HigℎLevel.uC_Port

VPullUp.Supply

(8)

tDO.fall=− RDO.switcℎ* CDO.load*ln Vin.LowLevel.uCPort

VPullUp.Supply

(9)

The timing diagram is shown in Figure 18.

STPM066S

SPI format and register mapping

DS12976 - Rev 2

page 27/67

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