8

Layout

8.1

Layout guidelines and considerations

In order to optimize the PCB layout, the following considerations should be taken into account:

•

SMD ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to

each supply rail pin. A 100 nF capacitor must be placed between VDD and GND and between VH_x and

GNDISO_x, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to

provide local storage for pulsed current a second capacitor with value in the range between 1 µF and 10 µF

should also be placed close to the supply pins.

–

As a good practice it is suggested to add filtering capacitors close to logic inputs of the device (INA,

INB, BRAKE, SD), in particular for fast switching or noisy applications.

•

The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop

area and inductance that might bring about noise or ringing.

•

To avoid degradation of the isolation between the primary and secondary side of the driver, there should not

be any trace or conductive area below the driver.

•

If the system has multiple layers, it is recommended to connect the VH_x and GNDISO_x pins to internal

ground or power planes through multiple vias of adequate size. These vias should be located close to the IC

pins to maximize thermal conductivity.

8.2

Layout example

An example of STGAP2HD suggested half-bridge with negative gate driving PCB layout is shown in Figure 7;

the main signals have been highlighted by different colors. It is recommended to follow this example for proper

positioning and connection of filtering capacitors.

Figure 7. Suggested PCB layout for half-bridge configuration with negative driving voltage

GHS

SHS

DLS

Roff

Roff

Ron

Ron

DHS

SLS

GLS

CVH

CVHL

RPU

RIN

RIN

RIN

RIN

CVHL

CVH

CL

CG

CVDD

CIN

CG

TOP

BOTTOM

CVDD

RPU

CIN

CIN

CIN

CL

STGAP2HD

Layout

DS13652 - Rev 2

page 14/24