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9FGP202 Datasheet(PDF) 13 Page - Renesas Technology Corp |
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9FGP202 Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 20 page ![]() 9FGP202A FREQUENCY TIMING GENERATOR FOR PERIPHERALS IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS 13 9FGP202A REV D 070511 SMB us Table: CPU Frequency Select and Spread Spectrum C ontrol Register Byte 0 Name Control Function Type 0 1 PWD Bit 7 Reserved Reserved RW 0 Bit 6 Reserved Reserved R ev 0.20 0 Bit 5 Reserved Reserved RW 0 Bit 4 DOT96 SS_EN DOT96 Spread Spectrum Enable RW D isable Enable 0 Bit 3 CPU SS_EN CPU Spread Spectrum Enable RW 0 Bit 2 CPU FS2 CPU Freq Select Bit 2 RW 0 Bit 1 CPU FS1 CPU Freq Select Bit 1 RW 1 Bit 0 CPU FS0 CPU Freq Select Bit 0 RW 0 SMB us Table: RMII Output Control R egister Byte 1 Name Control Function Type 0 1 PWD Bit 7 RMII_7 Enable RMII_7 Output Control RW D isable Enable 1 Bit 6 RMII_6 Enable RMII_6 Output Control RW D isable Enable 1 Bit 5 RMII_5 Enable RMII_5 Output Control RW D isable Enable 1 Bit 4 RMII_4 Enable RMII_4 Output Control RW D isable Enable 1 Bit 3 RMII_3 Enable RMII_3 Output Control RW D isable Enable 1 Bit 2 RMII_2 Enable RMII_2 Output Control RW D isable Enable 1 Bit 1 RMII_1 Enable RMII_1 Output Control RW D isable Enable 1 Bit 0 RMII_0 Enable RMII_0 Output Control RW D isable Enable 1 SMB us Table: DOT, CPU, 32.768K Hz, 25MHz and 33.33MHz Outputs Control R egister Byte 2 Name Control Function Type 0 1 PWD Bit 7 CPUCLK PD Drive Mode Driven in PD RW Driven Hi-Z 0 Bit 6 D OT96SS PD Drive Mode Driven in PD RW Driven Hi-Z 0 Bit 5 33.33MH z Enable 33.33MHz Output Control RW D isable Enable 1 Bit 4 25MH z_1 Enable 25MHz_1 Output Control RW D isable Enable 1 Bit 3 25MH z_0 Enable 25MHz_0 Output Control RW D isable Enable 1 Bit 2 32.768kHz Enable 32.768KHz Output Control RW D isable Enable 1 Bit 1 CPUCLK Enable CPUCLK Output Control RW D isable Enable 1 Bit 0 DOT96SS Enable D OT96SS Output Control RW D isable Enable 1 SMB us Table: DOT96 Frequency Select and Spread Spectrum Control Register Byte 3 Name Control Function Type 0 1 PWD Bit 7 Reserved Reserved RW 0 Bit 6 Reserved Reserved RW 0 Bit 5 Reserved Reserved RW 0 Bit 4 Reserved Reserved RW 0 Bit 3 DOT96SS FS3 DOT96 Freq Select Bit 3 RW 0 Bit 2 DOT96SS FS2 DOT96 Freq Select Bit 2 RW 0 Bit 1 DOT96SS FS1 DOT96 Freq Select Bit 1 RW 0 Bit 0 DOT96SS FS0 DOT96 Freq Select Bit 0 RW 0 SMB us Table: RMII Strength C ontrol Register Byte 4 Name Control Function Type 0 1 PWD Bit 7 RMII_7 Str RMII_7 Strength Control RW 1-Load (1X) 2-Loads (2X) 0 Bit 6 RMII_6 Str RMII_6 Strength Control RW 1-Load (1X) 2-Loads (2X) 0 Bit 5 RMII_5 Str RMII_5 Strength Control RW 1-Load (1X) 2-Loads (2X) 0 Bit 4 RMII_4 Str RMII_4 Strength Control RW 1-Load (1X) 2-Loads (2X) 0 Bit 3 RMII_3 Str RMII_3 Strength Control RW 1-Load (1X) 2-Loads (2X) 0 Bit 2 RMII_2 Str RMII_2 Strength Control RW 1-Load (1X) 2-Loads (2X) 0 Bit 1 RMII_1 Str RMII_1 Strength Control RW 1-Load (1X) 2-Loads (2X) 0 Bit 0 RMII_0 Str RMII_0 Strength Control RW 1-Load (1X) 2-Loads (2X) 0 SMB us Table: 32.768K Hz, 25Mhz and 33.33MHz Strength Control Register Byte 5 Name Control Function Type 0 1 PWD Bit 7 Reserved Reserved RW Reserved 0 Bit 6 Reserved Reserved RW Reserved 0 Bit 5 33.33MHz Str 33.33MH z Strength Control RW 1-Load (1X) 2-Loads (2X) 1 Bit 4 25MHz_1 Str 25MH z_1 Strength Control RW 1-Load (1X) 2-Loads (2X) 1 Bit 3 25MHz_0 Str 25MH z_1 Strength Control RW 1-Load (1X) 2-Loads (2X) 1 Bit 2 32.768kHz Str 32.768kHz Strength Control RW 1-Load (1X) 2-Loads (2X) 1 Bit 1 Reserved Reserved RW Reserved 0 Bit 0 Reserved Reserved RW Reserved 0 25 - - 37 7,8 - 3,4 22 17 - - - Pin # 28 29 32 33 16 - Reserved - Reserved Reserved - - 24 36 - - - 13 - 6 5 - - 32 29 28 25 Reserved Reserved See Table 2: DOT Frequency Selection Table 33 Reserved See Table 1: CPU Frequency Selection Table - - 22 17 16 13 - - 24 Pin # Reserved Pin # Pin # Pin # Pin # 37 36 |
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