IDT®

Frequency Timing Generator for Peripherals

1664—07/16/14

9FGP205

Frequency Timing Generator for Peripherals

13

SMBus Table: CPU Frequency Select and Spread Spectrum Control Register

Byte 0

Name

Control Function

Type0

1

PWD

Bit 7

WOL_STOP_EN

Enables 25M in Power Down

RW

Disable

Enabled

1

Bit 6

Reserved

Reserved

RW

0

Bit 5

Reserved

Reserved

RW

0

Bit 4

DOT96 SS_EN

DOT96 Spread Spectrum Enable

RW

Disable

Enable

0

Bit 3

CPU SS_EN

CPU Spread Spectrum Enable

RW

0

Bit 2

CPU FS2

CPU Freq Select Bit 2

RW

1

Bit 1

CPU FS1

CPU Freq Select Bit 1

RW

0

Bit 0

CPU FS0

CPU Freq Select Bit 0

RW

1

SMBus Table: RMII Output Control Register

Byte 1

Name

Control Function

Type0

1

PWD

Bit 7

RMII_5 Enable

RMII_7 Output Control

RW

Disable

Enable

1

Bit 6

RMII_4 Enable

RMII_6 Output Control

RW

Disable

Enable

1

Bit 5

RMII_3 Enable

RMII_5 Output Control

RW

Disable

Enable

1

Bit 4

RMII_2 Enable

RMII_4 Output Control

RW

Disable

Enable

1

Bit 3

RMII_1 Enable

RMII_3 Output Control

RW

Disable

Enable

1

Bit 2

RMII_0 Enable

RMII_2 Output Control

RW

Disable

Enable

1

Bit 1

RGMII_1 Enable

RGMII_1 Output Control

RW

Disable

Enable

1

Bit 0

RGMII_0 Enable

RGMII_0 Output Control

RW

Disable

Enable

1

SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register

Byte 2

Name

Control Function

Type0

1

PWD

Bit 7

CPUCLK PD Drive Mode

Driven in power down

RW

Driven

Hi-Z

1

Bit 6

DOT96SS PD Drive Mode

Driven in power down

RW

Driven

Hi-Z

1

Bit 5

33.33MHz Enable

33.33MHz Output Control

RW

Disable

Enable

1

Bit 4

25MHz_1 Enable

25MHz_1 Output Control

RW

Disable

Enable

1

Bit 3

25MHz_0 Enable

25MHz_0 Output Control

RW

Disable

Enable

1

Bit 2

32.768kHz Enable

32.768KHz Output Control

RW

Disable

Enable

1

Bit 1

CPUCLK Enable

CPUCLK Output Control

RW

Disable

Enable

1

Bit 0

DOT96SS Enable

DOT96SS Output Control

RW

Disable

Enable

1

SMBus Table: DOT96 Frequency Select and Spread Spectrum Control Register

Byte 3

Name

Control Function

Type0

1

PWD

Bit 7

RMII_5 WOL_STOP

RMII_5 runs in power down

RW

Off

Runs

0

Bit 6

RMII_4 WOL_STOP

RMII_4 runs in power down

RW

Off

Runs

0

Bit 5

RMII_3 WOL_STOP

RMII_3 runs in power down

RW

Off

Runs

0

Bit 4

RMII_2 WOL_STOP

RMII_2 runs in power down

RW

Off

Runs

1

Bit 3

DOT96SS FS3

DOT96 Freq Select Bit 3

RW

0

Bit 2

DOT96SS FS2

DOT96 Freq Select Bit 2

RW

0

Bit 1

DOT96SS FS1

DOT96 Freq Select Bit 1

RW

0

Bit 0

DOT96SS FS0

DOT96 Freq Select Bit 0

RW

0

SMBus Table: RMII Strength Control Register

Byte 4

Name

Control Function

Type0

1

PWD

Bit 7

RMII_5 Str

RMII_5 Strength Control

RW

1-Load (1X) 2-Loads (2X)

0

Bit 6

RMII_4 Str

RMII_4 Strength Control

RW

1-Load (1X) 2-Loads (2X)

0

Bit 5

RMII_3 Str

RMII_3 Strength Control

RW

1-Load (1X) 2-Loads (2X)

0

Bit 4

RMII_2 Str

RMII_2 Strength Control

RW

1-Load (1X) 2-Loads (2X)

0

Bit 3

RMII_1 Str

RMII_1 Strength Control

RW

1-Load (1X) 2-Loads (2X)

0

Bit 2

RMII_0 Str

RMII_0 Strength Control

RW

1-Load (1X) 2-Loads (2X)

0

Bit 1

RMII_1 WOL_STOP

RMII_1 runs in power down

RW

Off

Runs

1

Bit 0

RMII_0 WOL STOP

RMII_0 runs in power down

RW

Off

Runs

1

17

Pin #

25

-

-

37

7,8

24

3,4

22

32

33

-

-

-

16

-

Reserved

-

-

-

24

36

28

29

-

28

29

13

25

6

5

-

-

32

29

28

25

See Table 2:

DOT Frequency Selection

Table

24

Pin #

Reserved

See Table 1:

CPU Frequency Selection

Table

Pin #

Pin #

Pin #

33

32

33