9QXL2000C datasheet(9/23 Pages) RENESAS

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R31DS0118EU0101 Rev.1.01

Page 9

Apr 5, 2022

9QXL2000C Datasheet

Input High Voltage

VIH

Tri-level inputs.

2.2

VDD + 0.3

Input Mid Voltage

VIM

Tri-level inputs.

1.2

VDD/2

1.8

Input Low Voltage

VIL

Tri-level inputs.

GND - 0.3

0.8

Input Current

IIH

Single-ended inputs unless otherwise listed.

Clock Inputs are listed in Table 2. VIN = VDD.

μA

CKPWRGD_PD#, VIN = VDD.

-1

μA

SADR[1:0]_tri, VIN = VDD.

μA

Input Current

IIL

Single-ended inputs unless otherwise listed.

Clock Inputs are listed in Table 2. VIN = GND.

-3

μA

CKPWRGD_PD#, VIN = GND.

-35

-20

μA

SADR[1:0]_tri, VIN = GND.

-35

-20

μA

Input Frequency

FIN

400

MHz

Pin Inductance [1]

Lpin

Capacitance

CIN

Logic inputs, except DIF_IN.

1.5

CINDIF_IN DIF_IN differential clock inputs. [1][2]

1.5

2.7

COUT

Output pin capacitance.

Clk Stabilization

TSTAB

Measured from when all power supplies have

reached > 90% of nominal voltage to the first

stable clock edge on the output.

CKPWRGD_PD# tied to VDD in this case. [1][3]

1.2

VDD stable, measured from de-assertion of

CKPWRGD_PD#. [1][3]

0.3

1.0

OE# Latency [1][3][4]

tLATOE#

DIF start after OE# assertion.

DIF stop after OE# deassertion.

clocks

Tfall [3]

Fall time of control inputs.

Trise [3]

Rise time of control inputs.

1. Confirmed by design and characterization, not 100% tested in production.

2. DIF_IN input.

3. Control input must be monotonic from 20% to 80% of input swing.

4. Time from deassertion until outputs are > 200mV.

Table 3. Input/Supply/Common Parameters (Cont.)

Parameter

Symbol

Conditions

Minimum

Typical

Maximum

Unit

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