9UMS9633B datasheet(13/23 Pages) RENESAS

13 / 23 page

R31DS0110EU0100 Rev.1.00

Page 13

Jan 18, 2022

9UMS9633B Datasheet

Table 7. Byte 0 – PLL and Divider Enable Register

Bit(s)

Name

Description

Type

Default

PLL1 Enable

This bit controls whether the PLL driving the

CPU and SRC clocks is enabled or not.

0 = Disabled

1 = Enabled

PLL2 Enable

This bit controls whether the PLL driving the

DOT and clock is enabled or not.

0 = Disabled

1 = Enabled

PLL3 Enable

This bit controls whether the PLL driving the LCD

clock is enabled or not.

0 = Disabled

1 = Enabled

Reserved

CPU Divider Enable

This bit controls whether the CPU output divider

is enabled or not.

NOTE: This bit should be automatically set to ‘0’

if bit 7 is set to ‘0’.

0 = Disabled

1 = Enabled

SRC Output Divider

Enable

This bit controls whether the SRC output divider

is enabled or not.

NOTE: This bit should be automatically set to ‘0’

if bit 7 is set to ‘0’.

0 = Disabled

1 = Enabled

LCD Output Divider

Enable

This bit controls whether the LCD output divider

is enabled or not.

NOTE: This bit should be automatically set to ‘0’

if bit 5 is set to ‘0’.

0 = Disabled

1 = Enabled

DOT Output Divider

Enable

This bit controls whether the DOT output divider

is enabled or not.

NOTE: This bit should be automatically set to ‘0’

if bit 6 is set to ‘0’.

0 = Disabled

1 = Enabled

Table 8. Byte 1 – PLL SS Enable/Control Register

Bit(s)

Name

Description

Type

Default

PLL1 SS Enable

This bit controls whether PLL1 has spread

enabled or not. Spread spectrum for PLL1 is set

at -0.5% down-spread. Note that PLL1 drives the

CPU and SRC clocks.

0 = Disabled

1 = Enabled

PLL3 SS Enable

This bit controls whether PLL3 has spread

enabled or not. Note that PLL3 drives the SSC

clock, and that the spread spectrum amount is

set in bits 3-5.

0 = Disabled

1 = Enabled

PLL3 FS Select

These 3 bits select the frequency of PLL3 and

the SSC clock when Byte 1 Bit 6 (PLL3 Spread

Spectrum Enable) is set.

See LCD Spread Select (Pin

20/21) table

Reserved

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