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ICS9UMS9001 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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ICS9UMS9001 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 16 page  IDT® PC MAIN CLOCK - CK540 1247C—06/16/11 Advance Information 9UMS9001 PC MAIN CLOCK - CK540 11 Byte 0 FS Readback, SS Enable, STOP Control Register Bit Pin Name Description Type 0 1 Default 7 - FSLC CPU Freq. Sel. Bit MSB RW Latch 6 FSLB CPU Freq. Sel. Bit LSB RW Latch 5 CPU_SS_EN Spread spectrum enable for CPU/SRC/PCI outputs RW SS Disabled SS Enabled 1 4 LCD_Enable Turns On LCD PLL RW Off On 1 3 SRC3_STOP SRC 3 Stop Control RW 0 2 SRC2_STOP SRC 2 Stop Control RW 0 1 SRC1_STOP SRC 1 Stop Control RW 0 0 SRC0_STOP SRC 0 Stop Control RW 0 Byte 1 LCD Quick Config and CPU Stop ControlRegister Bit Pin Name Description Type 0 1 Default 7 CPU_ITP_STOP CPU_ITP Stop Control RW 0 6 CPU1_STOP CPU1 Stop Control RW 1 5 CPU0_STOP CPU0 Stop Control RW 1 4 LCD_SS_EN Turns on SS for LCD PLL RW Off On 1 3 LCD_SSC_SEL Select down or center SSC RW Down spread Center spread 0 2 LCD_CF2 PLL3 Quick Config Bit 2 RW 0 1 LCD_CF1 PLL3 Quick Config Bit 1 RW 0 0 LCD_CF0 PLL3 Quick Config Bit 0 RW 1 Byte 2 Output Enable and Stop Control Register Bit Pin Name Description Type 0 1 Default 7 PCI_F2_STOP Free running PCI Stop Control RW 0 6 PCI1_STOP PCI1 Stop Control RW 1 5 PCI0_STOP PCI 0 Stop Control RW 1 4 REF_OE Output enable for REF RW Output Disabled Output Enabled 1 3 USB_OE Output enable for USB RW Output Disabled Output Enabled 1 2 PCIF2_OE Output enable for PCI2 RW Output Disabled Output Enabled 1 1 PCI1_OE Output enable for PCI1 RW Output Disabled Output Enabled 1 0 PCI0_OE Output enable for PCI0 RW Output Disabled Output Enabled 1 Byte 3 Output Enable Register Bit Pin Name Description Type 0 1 Default 7 CPU_ITP_OE Output enable for CPU_ITP RW Output Disabled Output Enabled 1 6 CPU1_OE Output enable for CPU1 RW Output Disabled Output Enabled 1 5 CPU0_OE Output enable for CPU0 RW Output Disabled Output Enabled 1 4 Reserved Reserved RW 0 3 SRC3_OE Output enable for SRC4 RW Output Disabled Output Enabled 1 2 SRC2_OE Output enable for SRC4 RW Output Disabled Output Enabled 1 1 SRC1_OE Output enable for SRC4 RW Output Disabled Output Enabled 1 0 SRC0_OE Output enable for SRC4 RW Output Disabled Output Enabled 1 Byte 4 Output Enable and CLKREQ# Control Register Bit Pin Name Description Type 0 1 Default 7 DOT96_OE Output enable for DOT96 RW Output Disabled Output Enabled 1 6 LCD100_OE Output enable for LCD100 RW Output Disabled Output Enabled 1 5 Reserved Reserved RW 0 4 Reserved Reserved RW 0 3 SRC3_CR SRC3 CLKREQ3# Enable RW 0 2 SRC2_CR SRC2 CLKREQ2# Enable RW 0 1 SRC1_CR SRC1 CLKREQ1# Enable RW 0 0 SRC0_CR SRC0 CLKREQ0# Enable RW 0 See Frequency Select Table Not controlled by CLKREQ# Controlled by CLKREQ# Free Running Stops with PCI_STOP# assertion See Table 2: LCD Quick Configuration Free Running Stops with CPU_STOP# assertion Stops with PCI_STOP# Assertion Free Running |
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