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©2020 Renesas Electronics Corporation

February 19, 2020

9SQL4952/9SQL4954/9SQL4958 Datasheet

Power Management

1 The output state is set by B11[1:0] (Low/Low default).

2 REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is disabled unless Byte3[5] = 1, in which

case REF is running.

3 Input polarities defined at default values.

4 See SMBus description for Byte 3, bit 4.

Test Loads

Figure 4. Single-ended Output Test Load

Table 15. Power Management 3

CKPWRGD_PD#

SMBus OE bit

OEx# Pin

Differential Output

REF

True O/P

Comp. O/P

0X

X

Low 1

Low 1

Hi-Z 2

1

1

0

Running

Running

Running

11

1

Disabled 1

Disabled 1

Running

10

X

Disabled 1

Disabled 1

Disabled 4

Table 16. SMBus Address Selection

SADR

Address

+ Read/Write Bit

State of SADR on first

application of CKPWRGD_PD#

0

1101000

X

1

1101010

X

Table 17. Terminations for Single-ended Output

Clock Source

Device Under Test (DUT)

Rs (Ω)

Zo (Ω)

L (cm)

CL (pF)

N/A

9SQL495x

33

50

12.7

4.7

Rs

CL

Zo

L

Test

Point

DUT

REFCLK