SL2ICS20 datasheet(4/12 Pages) NXP

4 / 12 page

Philips Semiconductors

Product Specification Rev.3.0 December 2002

Bumped Wafer Specification

SL2 ICS 20

6 CHIP ORIENTATION AND BONDPAD LOCATIONS

PAD(center)

x [µm]

y [µm]

0.0

665.0

-30.0

TESTIO

687.0

-632.0

VSS

-93.0

-385.0

Not to scale!

(1) X-Scribeline width:

tbd µm

(7) LB bump edge to chip edge, y-length:

69[+7] µm

(2) Y-Scribeline width:

tbd µm

(8) LB bump edge to chip edge, x-length:

39[+7] µm

(3) Chip step, x-length:

X-Scribeline + 900 µm

(9) TESTIO bump edge to chip edge, x-length: 32[+7] µm

(4) Chip step, y-length:

Y-Scribeline + 780 µm

(10) TESTIO bump edge to chip edge, y-length:32[+7] µm

(5) LA bump edge to chip edge, y-length:

39[+7] µm

(11) VSS bump edge to chip edge, y-length: 279[+7] µm

(6) LA bump edge to chip edge, x-length:

104[+7] µm

(12) VSS bump edge to chip edge, x-length:

26[+7] µm

[+7µm] ...for pad edge to chip edge!

Figure 1

(1)

TESTIO

VSS

(4)

(3)

(5)

(6)

(2)

(9)

Widths and lengths are measured from metal to metal.

(12)

(11)

(10)

(8)

(7)

SL2ICS20 Datasheet(PDF) 4 Page - NXP Semiconductors

SL2ICS20 Datasheet(HTML) 4 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Link URL