6.42

71V30S/L

High-Speed 1K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

13

Functional Description

The IDT71V30 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT71V30 has an automatic power down

featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry

that permits the respective port to go into a standby mode when not

selected (CE = VIH). When a port is enabled, access to the entire

memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt

flag (INTL) is asserted when the right port writes to memory location

3FE (HEX), where a write is defined as the CE = R/W = VIL per Truth

Table II. The left port clears the interrupt by accessing address location

3FE access with CER = OER = VIL, R/W is a "don't care". Likewise, the

right port interrupt flag (INTR) is asserted when the left port writes to

memory location 3FF (HEX) and to clear the interrupt flag (INTR), the

right port must access the memory location 3FF. The message (8 bits)

at3FEor3FFisuser-defined,sinceitisanaddressableSRAMlocation.

Iftheinterruptfunctionisnotused,addresslocations3FEand3FFarenot

used as mail boxes, and are part of the random access memory. Refer

to Table II for the interrupt operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

SRAM have accessed the same location at the same time. It also

allows one of the two accesses to proceed and signals the other side

that the SRAM is “Busy”. The BUSY pin can then be used to stall the

access until the operation on the other side is completed. If a write

operation has been attempted from the side that receives a BUSY

indication, the write signal is gated internally to prevent the write from

proceeding.

The use of BUSY logic is not required or desirable for all applica-

tions. In some cases it may be useful to logically OR the BUSY outputs

together and use any BUSY indication as an interrupt source to flag the

event of an illegal or illogical operation.