AT45DQ321 datasheet(13/81 Pages) RENESAS

13 / 81 page

AT45DQ321

DS-45DQ321-031G–DFLASH–2/2022

To load data into a buffer using the binary buffer size (512 bytes), an opcode of 44h for Buffer 1 or 47h for Buffer 2, must

be clocked into the device followed by 15 dummy bits and 9 buffer address bits (BFA8 - BFA0). The 9 buffer address bits

specify the first byte in the buffer to be written.

After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If

the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to

be loaded into the buffer until a low-to-high transition is detected on the CS pin.

6.4

Buffer to Main Memory Page Program with Built-In Erase

The Buffer to Main Memory Page Program with Built-In Erase command allows data that is stored in one of the SRAM

buffers to be written into an erased or programmed page in the main memory array. It is not necessary to pre-erase the

page in main memory to be written because this command will automatically erase the selected page prior to the

program cycle.

To perform a Buffer to Main Memory Page Program with Built-In Erase using the standard DataFlash page size

(528 bytes), an opcode of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three address

bytes comprised of 1 dummy bit, 13 page address bits (PA12 - PA0) that specify the page in the main memory to be

written, and 10 dummy bits.

To perform a Buffer to Main Memory Page Program with Built-In Erase using the binary page size (512 bytes), an opcode

of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three address bytes comprised of

2 dummy bits, 13 page address bits (A21 - A9) that specify the page in the main memory to be written, and 9 dummy bits.

When a low-to-high transition occurs on the CS pin, the device will first erase the selected page in main memory (the

erased state is a Logic 1) and then program the data stored in the appropriate buffer into that same page in main

memory. Both the erasing and the programming of the page are internally self-timed and should take place in a

maximum time of t

EP. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.

The device also incorporates an intelligent erase and program algorithm that can detect when a byte location fails to

erase or program properly. If an erase or programming error arises, it will be indicated by the EPE bit in the Status

6.5

Buffer to Main Memory Page Program without Built-In Erase

The Buffer to Main Memory Page Program without Built-In Erase command allows data that is stored in one of the SRAM

buffers to be written into a pre-erased page in the main memory array. It is necessary that the page in main memory to be

written be previously erased in order to avoid programming errors.

To perform a Buffer to Main Memory Page Program without Built-In Erase using the standard DataFlash page size (528

bytes), an opcode of 88h for Buffer 1 or 89h for Buffer 2 must be clocked into the device followed by three address bytes

comprised of 1 dummy bit, 13 page address bits (PA12 - PA0) that specify the page in the main memory to be written,

and 10 dummy bits.

To perform a Buffer to Main Memory Page Program using the binary page size (512 bytes), an opcode of 88h for Buffer

1 or 89h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 2 dummy bits, 13

page address bits (A21 - A9) that specify the page in the main memory to be written, and 9 dummy bits.

When a low-to-high transition occurs on the CS pin, the device will program the data stored in the appropriate buffer into

the specified page in the main memory. The page in main memory that is being programmed must have been previously

erased using one of the erase commands (Page Erase, Block Erase, Sector Erase, or Chip Erase). The programming of

the page is internally self-timed and should take place in a maximum time of tP. During this time, the RDY/BUSY bit in the

Status Register will indicate that the device is busy.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program

properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

AT45DQ321 Datasheet(PDF) 13 Page - Renesas Technology Corp

AT45DQ321 Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL