CD4060BMS

FN3317 Rev 0.00

Page 6 of 9

December 1992

Logic Diagram

TABLE 7. TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS

MIL-STD-883

METHOD

TEST

READ AND RECORD

PRE-IRRAD

POST-IRRAD

PRE-IRRAD

POST-IRRAD

Group E Subgroup 2

5005

1, 7, 9

Table 4

1, 9

Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION

OPEN

GROUND

VDD

9V

 -0.5V

OSCILLATOR

50kHz

25kHz

Static Burn-In 1 Note 1

1 - 7, 9, 10, 13 - 15

8, 11, 12

16

Static Burn-In 2 Note 1

1 - 7, 9, 10, 13 - 15

8

11, 12, 16

Dynamic Burn-In Note 1

-

8, 12

16

1 - 7, 9, 10, 13 - 15

11

-

Irradiation Note 2

1 - 7, 9, 10, 13 - 15

8

11, 12, 16

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K

 5%, VDD = 18V  0.5V

2. Each pin except VDD and GND will have a series resistor of 47K

5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 

0.5V

FF2-FF13

FF1

FF14

ø1 Q1

ø1 Q1

Q13

ø2

ø2

Q13

Q14

ø14

ø14

Q14

12

11

10

9

RESET

ø 0

ø 0

ø I

*

*

*

*

Q14

Q4 - Q10

Q12, Q13

*ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION

NETWORK

VDD

VSS

**R = HIGH DOMINATES (RESETS ALL STAGES)

***COUNTER ADVANCES ONE BINARY COUNT

ON EACH NEGATIVE - GOING TRANSITION

OF øI (AND øO)

**

***

DETAIL OF TYPICAL FLIP-FLOP STAGE

p

n

ø

ø

p

n

ø

ø

p

n

ø

ø

p

n

ø

ø

Q

Q

R

R