Figure 3. SPI Read register example

1 r

s

d

0 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0

Byte 0

Read 2 bytes

(b7 = 1)

0 0 0 0 0 0 0 0

SPI_MOSI

SPI_MISO

SPI_CS

SPI_CLK

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

Byte 3 address

lsb (0x19)

Byte 1 address

msb (0xD4)

Byte 2

(0x00)

Wait cycle

(b0 = 0)

ACK cycle

(b0 = 1)

LSB content

register

D4_0019 =

0x20

MSB content

register

D4_001A=

0x00

Bit indicating end of

Wait cycle (b0 = 1)

Bit indicating Wait cycle

(b0 = 0)

3.1.3

Protocol flow control for SPI write access

Following the standard specification, the TPM is authorized to insert 1 or more Wait states before acknowledging

the write access. A Wait state is low state (0) sent on the SPI_MISO pin by the TPM. An Acknowledgment is a

byte, whose last bit is ‘1’, sent on the SPI_MISO pin by the TPM.

Figure 4. SPI write register example

0 r

s

d

0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

SPI_CS

SPI_CLK

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

Bit indicating

Wait cycle (b0 =0)

Bit indicating end of Wait

cycle (b0 = 1)

Wait cycle

(b0 = 0)

LSB content

register D4_0018

= 0x40

ACK cycle

(b0 = 1)

x x x x x x x x 0 1 0 0 0 0 0 0

Set command

Ready bit (0x40)

SPI_MOSI

SPI_MISO

Byte 3 address

Lsb (0x18)

Byte 2

(0x00)

Byte 1 address

Msb (0xD4)

Byte 0

Write 1 byte

(b7 = 1)

3.2

Register space addresses

The following table shows TPM register space starting from the base address 0xD4_0000.

ST33TPHF2XSPI

Register space addresses

DS14186 - Rev 1

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