REVISION B 3/25/15

83940D DATA SHEET

11

LOW SKEW, 1-TO-18

LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

LVPECL CLOCK INPUT INTERFACE

The PCLK /nPCLK accepts LVPECL, CML, SSTL and other

differential signals. Both VSWING and VOH must meet the VPP and

VCMR input requirements. Figures 2A to 2F show interface ex-

amples for the PCLK/nPCLK input driven by the most common

driver types. The input interfaces suggested here are examples

only. If the driver is from another vendor, use their termination

recommendation. Please consult with the vendor of the driver

component to confirm the driver

termination requirements.

FIGURE 2A. PCLK/nPCLK INPUT DRIVEN

BY AN

OPEN COLLECTOR CML DRIVER

FIGURE 2B. PCLK/nPCLK INPUT DRIVEN

BY A

BUILT-IN PULLUP CML DRIVER

FIGURE 2C. PCLK/nPCLK INPUT DRIVEN

BY A

3.3V LVPECL DRIVER

FIGURE 2F.

PCLK/nPCLK INPUT DRIVEN

BY A

3.3V LVDS DRIVER

PCLK/nPCLK

2.5V

Zo = 60 Ohm

SSTL

HiPerClockS

PCLK

nPCLK

R2

120

3.3V

R3

120

Zo = 60 Ohm

R1

120

R4

120

2.5V

FIGURE 2E. PCLK/nPCLK INPUT DRIVEN

BY AN

SSTL DRIVER

HiPerClockS

PCLK

nPCLK

PCLK/nPCLK

3.3V

R2

50

R1

50

3.3V

Zo = 50 Ohm

CML

3.3V

Zo = 50 Ohm

3.3V

HiPerClockS

PCLK

nPCLK

R2

84

R3

125

Input

Zo = 50 Ohm

R4

125

R1

84

LVPECL

3.3V

3.3V

Zo = 50 Ohm

C2

R2

1K

R5

100

Zo = 50 Ohm

3.3V

3.3V

C1

R3

1K

LVDS

R4

1K

HiPerClockS

PCLK

nPCLK

R1

1K

Zo = 50 Ohm

3.3V

PCLK/nPCLK

3.3V

R5

100 - 200

3.3V

3.3V

HiPerClockS

PCLK

nPCLK

R1

125

PCLK/nPCLK

R2

125

R3

84

C1

C2

Zo = 50 Ohm

R4

84

Zo = 50 Ohm

R6

100 - 200

3.3V LVPECL

FIGURE 2D. PCLK/nPCLK INPUT DRIVEN

BY A

3.3V LVPECL DRIVER WITH AC COUPLE