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VN9D30Q100F Datasheet(PDF) 21 Page - STMicroelectronics |
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VN9D30Q100F Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 100 page ![]() Table 18. Operating codes OC1 OC0 Meaning 0 0 Write operation 0 1 Read operation 1 0 Read and clear status operation 1 1 Read device information Write mode The write mode of the device allows to write the content of the input data byte into the addressed register (see list of registers in Section 1 ). Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. During the same sequence the outgoing data are shifted out MSB first on the falling edge of the CSN pin and the subsequent bits on the falling edge of the serial clock (SCK). The first byte corresponds to the Global Status Byte, second and third bytes to the previous content of the addressed register. Figure 9. SPI write operation 0 0 SDI SDO CSN MSB Address Command Byte (8 bits) Global Status Byte MSB LSB LSB MSB MSB (previous content of register) Data (16 bits) Data LSB LSB GADG1010171330PS Read mode The read mode of the device allows to read and to check the state of any register. Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The command byte allows to determine which register content is read, whilst the other two data bytes are "don’t care". In case of a read mode on an unused address, the global status/error byte on the SDO pin is followed by 0x0000 word. In order to avoid inconsistency between the Global Status byte and the Status register, the Status register contents are frozen during the SPI communication. VN9D30Q100F SPI protocol DS13246 - Rev 4 page 21/100 |
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