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SC80C31BCYA44 Datasheet(PDF) 15 Page - NXP Semiconductors |
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SC80C31BCYA44 Datasheet(HTML) 15 Page - NXP Semiconductors |
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15 / 30 page  Philips Semiconductors Product specification 80C31/80C51/87C51 CMOS single-chip 8-bit microcontrollers 1996 Aug 16 15 AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 1 Oscillator frequency Speed versions : C, G 3.5 16 MHz tLHLL 1 ALE pulse width 85 2tCLCL–40 ns tAVLL 1 Address valid to ALE low 22 tCLCL–40 ns tLLAX 1 Address hold after ALE low 32 tCLCL–30 ns tLLIV 1 ALE low to valid instruction in 150 4tCLCL–100 ns tLLPL 1 ALE low to PSEN low 32 tCLCL–30 ns tPLPH 1 PSEN pulse width 142 3tCLCL–45 ns tPLIV 1 PSEN low to valid instruction in4 82 3tCLCL–105 ns tPXIX 1 Input instruction hold after PSEN 0 0 ns tPXIZ 1 Input instruction float after PSEN 37 tCLCL–25 ns tAVIV 1 Address to valid instruction in4 207 5tCLCL–105 ns tPLAZ 1 PSEN low to address float 10 10 ns Data Memory tRLRH 2, 3 RD pulse width 275 6tCLCL–100 ns tWLWH 2, 3 WR pulse width 275 6tCLCL–100 ns tRLDV 2, 3 RD low to valid data in 147 5tCLCL–165 ns tRHDX 2, 3 Data hold after RD 0 0 ns tRHDZ 2, 3 Data float after RD 65 2tCLCL–60 ns tLLDV 2, 3 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 2, 3 Address to valid data in 397 9tCLCL–165 ns tLLWL 2, 3 ALE low to RD or WR low 137 239 3tCLCL–50 3tCLCL+50 ns tAVWL 2, 3 Address valid to WR low or RD low 122 4tCLCL–130 ns tQVWX 2, 3 Data valid to WR transition 13 tCLCL–50 ns tWHQX 2, 3 Data hold after WR 13 tCLCL–50 ns tQVWH 3 Data valid to WR high 287 7tCLCL–150 ns tRLAZ 2, 3 RD low to address float 0 0 ns tWHLH 2, 3 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns External Clock tCHCX 5 High time 20 20 tCLCL–tCLCX ns tCLCX 5 Low time 20 20 tCLCL–tCHCX ns tCLCH 5 Rise time 20 20 ns tCHCL 5 Fall time 20 20 ns Shift Register tXLXL 4 Serial port clock cycle time 750 12tCLCL ns tQVXH 4 Output data setup to clock rising edge 492 10tCLCL–133 ns tXHQX 4 Output data hold after clock rising edge 8 2tCLCL–117 ns tXHDX 4 Input data hold after clock rising edge 0 0 ns tXHDV 4 Clock rising edge to input data valid 492 10tCLCL–133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interfacing. |
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