DA7219 datasheet(57/129 Pages) RENESAS

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DA7219

Audio Codec with Advanced Accessory Detect

Datasheet

Revision 3.4

24-Dec-2021

CFR0011-120-00

57 of 128

11.6.5

Example Calculation of the Feedback Divider Setting

A codec is operating with Fs (sample rate) = 48 kHz and a reference input clock frequency of

12.288 MHz. The required output frequency = 98.304 MHz.

The reference clock input = 12.288 MHz, which falls in the range 10 MHz to 20 MHz, so pll_indiv will

be set to 0b010 (dividing the reference input frequency by four, see Table 43.

The formula for calculating the feedback divider is:

Feedback divider (F) = (VCO output frequency * input divider (pll_indiv)) / reference input clock

Feedback divider = (98.304 * 4) / 12.288 = 32

● pll_fbdiv_integer (holding the seven integer bits) = 0x20

● pll_fbdiv_frac_top (holding the top bits (MSB) of the fractional part of the divisor) = 0x00

● pll_fbdiv_frac_bot (holding the bottom bits (LSB) of the fractional part of the divisor) = 0x00

Table 44 shows example register settings that will configure the PLL when using a 13 MHz, 15 MHz

or 19.2 MHz clock. Any MCLK input frequency between 2 MHz and 54 MHz is supported. pll_indiv

must be used to reduce the PLL reference frequency to the usable range of 2 MHz to 5 MHz as

shown in Table 43.

Table 44: Example PLL Configurations

MCLK input

frequency (MHz)

System clock

frequency (MHz)

pll_mode

PLL_FRAC_TOP

PLL_FRAC_BOT

11.2896

0x01

0x19

0x45

12.288

0x01

0x07

0xEA

11.2896

0x01

0x02

0xB4

12.288

0x01

0x06

0xDC

19.2

11.2896

0x01

0x1A

0x1C

19.2

12.288

0x01

0x0F

0x5C

11.6.6

PLL SRM Mode (DAI Slave)

SRM mode enables the PLL output clock to be synchronized to the incoming WCLK signal on the

DAI. The SRM PLL mode is enabled by setting pll_mode = 10.

When using the DAI in slave mode with the SRM enabled, removing and re-applying the DAI

interface word clock WCLK may cause the PLL lock to be lost. To re-lock the PLL it is recommended

that you disable the SRM (pll_mode = 00), reset the PLL by re-writing to register PLL_INTEGER, and

then re-enable the SRM (pll_mode = 10) after the DAI WCLK has been reapplied.

When switching sample rates between 44.1 kHz and 48 kHz (or between the multiples of these

sample rates), SRM must be disabled and then re-enabled using register bit pll_mode.

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