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DA7282-00FVC Datasheet(PDF) 33 Page - Renesas Technology Corp

Part # DA7282-00FVC
Description  LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory
PDF  88 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA7282-00FVC Datasheet(HTML) 33 Page - Renesas Technology Corp

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DA7282
LRA/ERM Ultra-Low Power Haptic Driver with
Multiple Input Triggers and Integrated
Waveform Memory
Datasheet
Revision 3.1
10-Feb-2022
CFR0011-120-00
33 of 87
© 2022 Renesas Electronics
I
2C write to stop driving
I
2C writes to start driving
Write to register
OVERRIDE_VAL
Output starts
switching
Write
OPERATION_
MODE = 1
IDLE/STANDBY
DRIVE
Write
OPERATION_
MODE = 0
DA7282
stops
driving
Change
OVERRIDE_VAL
Drive
amplitude
changes
The allowable range
differs depending on
the state of
ACCELERATION_EN
Figure 13: Operation in DRO Mode
5.6.5.3
PWM Mode
Figure 14 shows how to operate the device in PWM mode.
1. Starting from either the IDLE or STANDBY state, apply a PWM signal to the GPI_0/PWM pin.
2. When ready to begin playback, set OPERATION_MODE = 2. The output will begin switching
after approximately 0.75 ms with a drive amplitude proportional to the duty cycle of the incoming
PWM signal.
3. While in the DRIVE state, update the duty cycle of the PWM signal to drive a new amplitude level
and create the desired envelope of the haptic sequence. If the duty cycle of the PWM signal falls
below the threshold set by FULL_BRAKE_THR, it is interpreted as a zero output drive level.
4. In order to stop driving, set OPERATION_MODE = 0. DA7282 will return to either the IDLE or
STANDBY state depending on the value of STANDBY_EN.
Note: The duty cycle of the PWM signal is interpreted differently depending on the value of
ACCELERATION_EN. If ACCELERATION_EN = 1, then zero drive corresponds to 50 % duty cycle
±
FULL_BRAKE_THR. If ACCELERATION_EN = 0, then zero drive corresponds to 0 % duty cycle +
FULL_BRAKE_THR. For further explanation, see Figure 31 and Figure 32.



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