DSPIC30F datasheet(55/248 Pages) MICROCHIP

55 / 248 page

 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 53

dsPIC30F

4.4.3

MODULO ADDRESSING

APPLICABILITY

Modulo addressing can be applied to the effective

address (EA) calculation associated with any W regis-

ter. It is important to realize that the address bound-

aries check for addresses less than, or greater than the

upper (for incrementing buffers), and lower (for decre-

menting buffers) boundary addresses (not just equal

to). Address changes may, therefore, jump over bound-

aries and still be adjusted correctly (see Section 4.4.4

for restrictions).

4.4.4

MODULO ADDRESSING

RESTRICTIONS

For an incrementing buffer, the circular buffer start

address (lower boundary) is arbitrary but must be at a

‘zero’ power-of-two boundary (see Section 4.4.1). For

a decrementing buffer, the circular buffer end address

is arbitrary but must be at a ‘ones’ boundary.

There are no restrictions regarding how much an EA

calculation can exceed the address boundary being

checked and still be successfully corrected.

Once

configured,

the

direction

successive

addresses into a buffer should not be changed.

Although all EAs will continue to be generated cor-

rectly, irrespective of offset sign, only one address

boundary is checked for each type of buffer. Thus, if a

buffer is set up to be an incrementing buffer by choos-

ing an appropriate starting address, then correction of

the effective address will be performed by the AGU at

the upper address boundary, but no address correction

will occur if the EA crosses the lower address bound-

ary. Similarly, for a decrementing boundary, address

correction will be performed by the AGU at the lower

address boundary, but no address correction will take

place if the EA crosses the upper address boundary.

The circular buffer pointer may be freely modified in

both directions without a possibility of out-of-range

address access only when the start address satisfies

the condition for an incrementing buffer (last ‘N’ bits are

zeroes) and the end address satisfies the condition for

a decrementing buffer (last ‘N’ bits are ones). Thus, the

modulo addressing capability is truly bidirectional only

for modulo-2 length buffers.

4.5

Bit-Reversed Addressing

Bit-reversed addressing is intended to simplify data re-

ordering for radix-2 FFT algorithms. It is supported by

the X WAGU only (i.e., for data writes only).

The modifier, which may be a constant value or register

contents, is regarded as having its bit order reversed. The

address source and destination are kept in normal order.

Thus, the only operand requiring reversal is the modifier.

4.5.1

BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-reversed addressing is enabled when:

BWM (W register selection) in the MODCON

cannot

accessed

using

bit-reversed

addressing) and

the BREN bit is set in the XBREV register and

the Addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2N bytes,

then the last ‘N’ bits of the data buffer start address

must be zeros.

XB<14:0> is the bit-reversed address modifier or ‘pivot

point’ which is typically a constant. In the case of an

FFT computation, its value is equal to half of the FFT

data buffer size.

When enabled, bit-reversed addressing will only be

executed for register indirect with pre-increment or

post-increment addressing and word sized data writes.

It will not function for any other Addressing mode or for

byte sized data, and normal addresses will be gener-

ated instead. When bit-reversed addressing is active,

the W address pointer will always be added to the

address modifier (XB) and the offset associated with

the Register Indirect Addressing mode will be ignored.

In addition, as word sized data is a requirement, the LS

bit of the EA is ignored (and always clear).

If bit-reversed addressing has already been enabled by

setting the BREN (XBREV<15>) bit, then a write to the

XBREV register should not be immediately followed by

an indirect read operation using the W register that has

been designated as the bit-reversed pointer.

Note:

The modulo corrected effective address is

written back to the register only when Pre-

Modify or Post-Modify Addressing mode is

used to compute the effective address.

When an address offset (e.g., [W7+W2]) is

used, modulo address correction is per-

formed but the contents of the register

remain unchanged.

Note:

All bit-reversed EA calculations assume

word sized data (LS bit of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note:

Modulo

addressing

and

bit-reversed

addressing should not be enabled together.

In the event that the user attempts to do

this, bit-reversed addressing will assume

priority when active for the X WAGU, and X

WAGU modulo addressing will be disabled.

However, modulo addressing will continue

to function in the X RAGU.

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