DSPIC30F datasheet(160/248 Pages) MICROCHIP

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dsPIC30F

DS70083G-page 158

Preliminary

 2004 Microchip Technology Inc.

20.2.6

LOW POWER RC OSCILLATOR

(LPRC)

The LPRC oscillator is a component of the Watchdog

Timer (WDT) and oscillates at a nominal frequency of

512 kHz. The LPRC oscillator is the clock source for

the Power-up Timer (PWRT) circuit, WDT, and clock

monitor circuits. It may also be used to provide a low

frequency clock source option for applications where

power consumption is critical and timing accuracy is

not required

The LPRC oscillator is always enabled at a Power-on

Reset because it is the clock source for the PWRT.

After the PWRT expires, the LPRC oscillator will

remain on if one of the following is TRUE:

• The Fail-Safe Clock Monitor is enabled

• The WDT is enabled

• The LPRC oscillator is selected as the system

clock via the COSC<2:0> control bits in the

OSCCON register

If one of the above conditions is not true, the LPRC will

shut-off after the PWRT expires.

20.2.7

FAIL-SAFE CLOCK MONITOR

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by appropriately

programming the FCKSM configuration bits (clock

switch and monitor selection bits) in the FOSC Device

Configuration register. If the FSCM function is enabled,

the LPRC internal oscillator will run at all times (except

during Sleep mode) and will not be subject to control by

the SWDTEN bit.

In the event of an oscillator failure, the FSCM will gen-

erate a clock failure trap event and will switch the sys-

tem clock over to the FRC oscillator. The user will then

have the option to either attempt to restart the oscillator

or execute a controlled shutdown. The user may decide

to treat the trap as a warm Reset by simply loading the

Reset address into the oscillator fail trap vector. In this

event, the CF (Clock Fail) status bit (OSCCON<3>) is

also set whenever a clock failure is recognized.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

If the oscillator has a very slow start-up time coming out

of POR, BOR or Sleep, it is possible that the PWRT

timer will expire before the oscillator has started. In

such cases, the FSCM will be activated and the FSCM

will initiate a clock failure trap, and the COSC<2:0> bits

are loaded with FRC oscillator selection. This will effec-

tively shut-off the original oscillator that was trying to

start.

The user may detect this situation and restart the

oscillator in the clock fail trap ISR.

Upon a clock failure detection, the FSCM module will

initiate a clock switch to the FRC oscillator as follows:

The COSC bits (OSCCON<14:12>) are loaded

with the FRC oscillator selection value.

CF bit is set (OSCCON<3>).

OSWEN control bit (OSCCON<0>) is cleared.

For the purpose of clock switching, the clock sources

are sectioned into four groups:

Primary

Secondary

Internal FRC

Internal LPRC

The user can switch between these functional groups

but cannot switch between options within a group. If the

primary group is selected, then the choice within the

group

always

determined

the

FPR<4:0>

configuration bits.

The OSCCON register holds the control and status bits

related to clock switching.

• COSC<1:0>: Read only status bits always reflect

the current oscillator group in effect.

• NOSC<2:0>: Control bits which are written to

indicate the new oscillator group of choice.

- On POR and BOR, COSC<2:0> and

NOSC<1:0> are both loaded with the

configuration bit values FOS<2:0>.

• LOCK: The LOCK status bit indicates a PLL lock.

• CF: Read only status bit indicating if a clock fail

detect has occurred.

• OSWEN: Control bit changes from a ‘0’ to a ‘1’

when a clock transition sequence is initiated.

Clearing the OSWEN control bit will abort a clock

transition in progress (used for hang-up

situations).

If configuration bits FCKSM<2:0> = 1x, then the clock

switching and Fail-Safe Clock monitoring functions are

disabled. This is the default configuration bit setting.

Note 1: OSC2 pin function is determined by the

Primary

Oscillator

mode

selection

(FPR<4:0>).

2: OSC1 pin cannot be used as an I/O pin

even if the secondary oscillator or an

internal clock source is selected at all

times.

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