FN8999 Rev.1.00

Page 13 of 17

Jun 6, 2018

HIP2105, HIP2106A

4. Application Information

4.

Application Information

4.1

MOSFET Selection

The parasitic inductances of the PCB and of the power devices’ packaging (both upper and lower MOSFETs) can

cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the

PHASE node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some

cases, it may overstress the upper MOSFET driver. Careful layout, proper selection of MOSFETs, and packaging

can go a long way toward minimizing such unwanted stress.

The D2-PAK, or D-PAK packaged MOSFETs, have large parasitic lead inductances and are not recommended

unless additional circuits are implemented to prevent the BOOT and PHASE pins from exceeding the device rating.

Low-profile MOSFETs, such as direct FETs and multi-source leads devices (SO-8, LFPAK, PowerPAK), have low

parasitic lead inductances and are preferred.

4.2

Layout Considerations

A good layout helps reduce the ringing on the switching node (PHASE) and significantly lowers the stress applied

to the output drives. Use the following advice for an optimized layout:

• Keep decoupling loops (VCC - GND and BOOT - PHASE) as short as possible.

• Minimize trace inductance, especially on low-impedance lines. All power traces (UGATE, PHASE, LGATE,

GND, VCC) should be short and wide, as much as possible.

• Minimize the inductance of the PHASE node. Ideally, place the source of the upper and the drain of the lower

MOSFET as close as thermally allowable.

• Minimize the current loop of the output and input power trains. Short the source connection of the lower

MOSFET to ground as close to the transistor pin as feasible. Place the input capacitors (especially ceramic

decoupling) as close to the drain of the upper and source of the lower MOSFETs as possible.

In addition, for heat spreading, place copper underneath the IC whether it has an exposed pad or not. The copper

area can be extended beyond the bottom area of the IC and/or connected to buried power ground plane(s) with

thermal vias. This combination of vias for vertical heat escape, extended copper plane, and buried planes improve

heat dissipation and allow the part to achieve its full thermal potential. Figures 11 and 12 show a layout example.

Figure 11. HIP2105DBEVAL1Z Top Layer

Figure 12. HIP2105DBEVAL1Z Bottom Layer