HIP6004A

FN4417 Rev.2.00

Page 10 of 13

November 2002

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic capacitors

for high frequency decoupling and bulk capacitors to supply the

current needed each time Q1 turns on. Place the small ceramic

capacitors physically close to the MOSFETs and between the

drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum input

voltage and a voltage rating of 1.5 times is a conservative

guideline. The RMS current rating requirement for the input

capacitor of a buck regulator is approximately 1/2 the DC load

current.

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX

or equivalent) may be needed. For surface mount designs,

solid tantalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rating.

These capacitors must be capable of handling the surge-

current at power-up. The TPS series available from AVX, and

the 593D series from Sprague are both surge current tested.

MOSFET Selection/Considerations

The HIP6004A requires 2 N-Channel power MOSFETs. These

should be selected based upon rDS(ON), gate supply

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss components;

conduction loss and switching loss. The conduction losses are

the largest component of power dissipation for both the upper

and the lower MOSFETs. These losses are distributed

between the two MOSFETs according to duty factor (see the

equations below). Only the upper MOSFET has switching

losses, since the Schottky rectifier clamps the switching node

before the synchronous rectifier turns on. These equations

assume linear voltage-current transitions and do not

adequately model power loss due the reverse-recovery of the

lower MOSFET’s body diode. The gate-charge losses are

dissipated by the HIP6004A and don't heat the MOSFETs.

However, large gate-charge increases the switching interval,

tSW which increases the upper MOSFET switching losses.

Ensure that both MOSFETs are within their maximum junction

temperature at high ambient temperature by calculating the

temperature rise according to package thermal-resistance

specifications. A separate heatsink may be necessary

depending upon MOSFET power, package type, ambient

temperature and air flow.

Standard-gate MOSFETs are normally recommended for use

with the HIP6004A. However, logic-level gate MOSFETs can

be used under special circumstances. The input voltage, upper

gate drive level, and the MOSFET’s absolute gate-to-source

voltage rating determine whether logic-level MOSFETs are

appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by a

bootstrap circuit from VCC. The boot capacitor, CBOOT

develops a floating supply voltage referenced to the PHASE

pin. This supply is refreshed each cycle to a voltage of VCC

less the boot diode drop (VD) when the lower MOSFET, Q2

turns on. Logic-level MOSFETs can only be used if the

MOSFET’s absolute gate-to-source voltage rating exceeds the

maximum voltage applied to VCC.

Figure 10 shows the upper gate drive supplied by a direct

connection to VCC. This option should only be used in

converter systems where the main input voltage is +5VDC or

less. The peak upper gate-to-source voltage is approximately

VCC less the input supply. For +5V main power and +12VDC

for the bias, the gate-to-source voltage of Q1 is 7V. A logic-

level MOSFET is a good choice for Q1 and a logic-level

MOSFET can be used for Q2 if its absolute gate-to-source

voltage rating exceeds the maximum voltage applied to VCC.

PUPPER = Io2 x rDS(ON) x D +

1

2

Io x VIN x tSW x FS

PLOWER = Io2 x rDS(ON) x (1 - D)

Where: D is the duty cycle = VOUT / VIN,

tSW is the switch ON time, and

FS is the switching frequency.

+12V

PGND

HIP6004A

GND

LGATE

UGATE

PHASE

BOOT

VCC

+5V OR +12V

NOTE:

NOTE:

VG-S VCC

CBOOT

DBOOT

Q1

Q2

+

-

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

VG-S  VCC -VD

D2

+ VD -