HIP6014

FN4420 Rev.2.00

Page 8 of 12

March 2000

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output filter (LO and CO), with a double pole

break frequency at FLC and a zero at FESR. The DC Gain of

the modulator is simply the input voltage (VIN) divided by the

peak-to-peak oscillator voltage

VOSC.

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

(internal to the HIP6014) and the impedance networks ZIN and

ZFB. The goal of the compensation network is to provide a

closed loop transfer function with the highest 0dB crossing

frequency (f0dB) and adequate phase margin. Phase margin is

the difference between the closed loop phase at f0dB and 180

degrees

 The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 7. Use these guidelines for

locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)

3. Place 2ND Zero at Filter’s Double Pole

4. Place 1ST Pole at the ESR Zero

5. Place 2ND Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Compensation Break Frequency Equations

Figure 8 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak due to the high Q factor of the output filter and is not shown

in Figure 8. Using the above guidelines should give a

Compensation Gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

compensation gain at FP2 with the capabilities of the error

amplifier. The Closed Loop Gain is constructed on the log-log

graph of Figure 8 by adding the Modulator Gain (in dB) to the

Compensation Gain (in dB). This is equivalent to multiplying the

modulator transfer function to the compensation transfer

function and plotting the gain.

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current. The

load transient requirements are a function of the slew rate

(di/dt) and the magnitude of the transient load current. These

requirements are generally met with a mix of capacitors and

careful layout.

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1

F ceramic

capacitors in the 1206 surface-mount package.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the equivalent series inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient

loading. Unfortunately, ESL is not a specified parameter.

Work with your capacitor supplier and measure the

capacitor’s impedance with frequency to select a suitable

component. In most cases, multiple electrolytic capacitors of

FLC

1

2



LO CO





----------------------------------------

=

FESR

1

2

 ESR CO





-----------------------------------------

=

FZ1

1

2

 R

2



C1



---------------------------------

=

FZ2

1

2



R1 R3

+

 C

3





----------------------------------------------------

=

FP1

1

2

 R

2

C1 C2



C1 C2

+

---------------------











-----------------------------------------------------

=

FP2

1

2

 R

3



C3



---------------------------------

=

100

80

60

40

20

0

-20

-40

-60

FP1

FZ2

10M

1M

100K

10K

1K

100

10

OPEN LOOP

ERROR AMP GAIN

FZ1

FP2

20LOG

FLC

FESR

COMPENSATION

FREQUENCY (Hz)

GAIN

20LOG

(VIN/VOSC)

MODULATOR

GAIN

(R2/R1)

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP

GAIN