HIP6500B datasheet(23/30 Pages) RENESAS

23 / 30 page

HIP6500B

FN4870 Rev 0.00

Page 8 of 15

May 2000

Functional Timing Diagrams

Figures 4 through 8 are timing diagrams, detailing the power

up/down sequences of all three outputs in response to the

status of the enable (EN3VDL, EN5VDL) and sleep-state pins

(S3, S5), as well as the status of the ATX supply.

The status of the EN3VDL and EN5VDL pins can only be

changed while in active (S0, S1) states, when the bias supply

(5VSB pin) is below POR level, or during chip shutdown (SS

pin shorted to GND); a status change of these two pins while in

a sleep state is ignored.

Not shown in these diagrams is the deglitching feature used to

protect against false sleep state tripping. Both S3 and S5 pins

are protected against noise by a 2

s filter (typically 1 - 4s).

This feature is useful in noisy computer environments if the

control signals have to travel over significant distances.

Additionally, the S3 pin features a 200

s delay in transitioning

to sleep states. Once the S3 pin goes low, an internal timer is

activated. At the end of the 200

s interval, if the S5 pin is low,

the HIP6502 switches into S5 sleep state; if the S5 pin is high,

the HIP6502 goes into S3 sleep state.

FIGURE 4. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR

EN3VDL = 1, EN5VDL = 1

5VSB

12V

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL

FIGURE 5. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR

EN3VDL = 1, EN5VDL = 0

5VSB

12V

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL

FIGURE 6. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR

EN3VDL = 0, EN5VDL = 1

5VSB

12V

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL

FIGURE 7. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR

EN3VDL = 0, EN5VDL = 0

5VSB

12V

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL

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