HIP6500BEVAL1 datasheet(24/30 Pages) RENESAS

24 / 30 page

HIP6500B

FN4870 Rev 0.00

Page 9 of 15

May 2000

Soft-Start Circuit

SOFT-START INTO SLEEP STATES (S3, S4/S5)

The 5VSB POR function initiates the soft-start sequence. An

internal 10

A current source charges an external capacitor.

The error amplifiers reference inputs are clamped to a level

proportional to the SS (soft-start) pin voltage. As the SS pin

voltage slews from about 1.25V to 2.5V, the input clamp allows

a rapid and controlled output voltage rise.

Figure 9 shows the soft-start sequence for the typical

application start-up in sleep state with all output voltages

enabled. At time T0 5VSB (bias) is applied to the circuit. At

time T1 the 5VSB surpasses POR level. An internal fast

charge circuit quickly raises the SS capacitor voltage to

approximately 1V, then the 10

A current source continues the

charging. The soft-start capacitor voltage reaches

approximately 1.25V at time T2, at which point the 3.3VSB

error amplifiers’ reference input starts its transition, causing the

output voltage to ramp up proportionally. The ramp-up

continues until time T3 when the 3.3VSB voltage reaches the

set value. After the 3.3VSB reached its set value, as the soft-

start capacitor voltage reaches approximately 2.75V, the

under-voltage monitoring circuit of this output is activated and

the soft-start capacitor is quickly discharged to approximately

1.25V. Following the 3ms (typical) time-out between T3 and

T4, the memory and enabling pins’ selection are latched in,

and the soft-start capacitor commences a second ramp-up

designed to smoothly bring up the remainder of the voltages

required by the system. At time T5 all voltages are within

regulation limits, and as the SS voltage reaches 2.75V, all the

UV monitors are activated and the SS capacitor is quickly

discharged to 1.25V, where it remains until the next transition.

FIGURE 8. 2.5/3.3VMEM, 3.3VSB AND VCLK TIMING DIAGRAM

5VSB

12V

DRV2

VSEN2

INTERNAL

DEVICE

3V3SB

VCLK

FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE

(ALL OUTPUTS ENABLED)

TIME

SOFT-START

(1V/DIV)

OUTPUT

(1V/DIV)

VOLTAGES

VOUT3 (3.3VDUAL)

VOUT2

VOUT5 (5VDUAL)

T1 T2

5VSB

(1V/DIV)

VOUT1 (3.3VSB)

(2.5VMEM)

VOUT4

(2.5VCLK)

FIGURE 10. SOFT-START INTERVAL IN ACTIVE STATE

(2.5/3.3VMEM OUTPUT SHOWN IN 2.5V SETTING)

TIME

OUTPUT

(1V/DIV)

VOLTAGES

INPUT VOLTAGES

(2V/DIV)

+5VIN

+12VIN

+5VSB

VOUT2, 4

VOUT3 (3.3VDUAL)

VOUT1 (3.3VSB)

VOUT5 (5VDUAL)

DLA PIN

(2V/DIV)

SOFT-START

(1V/DIV)

(2.5VMEM, 2.5VCLK)

+3.3VIN

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