HIP6502B

FN4871 Rev.0.00

Page 6 of 14

May 2000

Functional Pin Descriptions

3V3 (Pin 7)

Connect this pin to the ATX 3.3V output. This pin provides the

output current for the 2V5CLK pin, and is monitored for power

quality.

5VSB (Pin 2)

Provide a very well de-coupled 5V bias supply for the IC to this

pin by connecting it to the ATX 5VSB output. This pin provides

the output current for the VSEN1 and VSEN2 pins, as well as

the base current for Q2. The voltage at this pin is monitored for

power-on reset (POR) purposes.

5V (Pin 18)

Connect this pin to the ATX 5V output. This pin provides the

base bias current for Q1, and is monitored for power quality.

12V (Pin 17)

Connect this pin to the ATX 12V output. This pin provides the

gate bias voltage for Q3, Q5 and Q6, and is monitored for

power quality.

GND (Pin 11)

Signal ground for the IC. All voltage levels are measured with

respect to this pin.

S3 and S5 (Pins 9 and 10)

These pins switch the IC’s operating state from active (S0,

S1/S2) to S3 and S4/S5 sleep states. These are digital inputs

featuring internal 50k

 (typical) resistor pull-ups to 5VSB.

Internal circuitry de-glitches these pins for disturbances lasting

as long as 2

s (typically). Additional circuitry blocks any illegal

state transitions (such as S3 to S4/S5 or vice versa).

Respectively, connect S3 and S5 to the computer system’s

SLP_S3 and SLP_S5 signals.

MSEL (Pin 20)

Unconnected, this pin is held at approximately 1.9V by an

internal resistor divider. Pulling this pin below 0.9V enables the

2.5VMEM output, while pulling it above 2.9V enables the

3.3VMEM output (typical voltage levels). Leaving the pin open

enables both memory regulators.

EN5VDL (Pin 8)

This pin enables or disables sleep state support on the

5VDUAL output in response to S3 and S4/S5 requests. This is

a digital input pin whose status can only be changed during

active state operation or during chip shutdown (SS pin

grounded by external open-drain device or chip bias below

POR level). The input information is latched-in when entering

a sleep state, as well as following 5VSB POR release or exit

from shutdown. EN5VDL is internally pulled high through a

40

A current source.

FAULT (Pin 12)

In case of an undervoltage on any of the outputs or on any of

the monitored ATX outputs, or in case of an overtemperature

event, this pin is used to report the fault condition by being

pulled to 5VSB.

SS (Pin 16)

Connect this pin to a small ceramic capacitor (no less than

5nF; 0.1

F recommended). The internal soft-start (SS) current

source along with the external capacitor creates a voltage

ramp used to control the ramp-up of the output voltages.

Pulling this pin low with an open-drain device shuts down all

the outputs as well as force the FAULT pin low. The CSS

capacitor is also used to provide a controlled voltage slew rate

during active-to-sleep transitions on the 3.3VDUAL, and VMEM

outputs.

VSEN2 (Pin 1)

Connect this pin to the 2.5V memory output (VOUT2). In sleep

states, this pin is regulated to 2.5V through an internal pass

transistor capable of delivering 300mA (typically). The active-

state voltage at this pin is regulated through an external NPN

transistor connected at the DRV2 pin. During all operating

states, the voltage at this pin is monitored for under-voltage

events.

DRV2 (Pin 19)

Connect this pin to the base of a suitable NPN transistor. This

pass transistor regulates the 2.5V output from the ATX 3.3V

during active states operation.

3V3DL (Pin 5)

Connect this pin to the 3.3V dual/stand-by output (VOUT3). In

sleep states, the voltage at this pin is regulated to 3.3V; in

active states, ATX 3.3V output is delivered to this node through

a fully on N-MOS transistor. During all operating states, this pin

is monitored for under-voltage events.

3V3DLSB (Pin 4)

Connect this pin to the base of a suitable NPN transistor. In

sleep state, this transistor is used to regulate the voltage at the

3V3DL pin to 3.3V.

DLA (Pin 13)

Connect this pin to the gates of suitable N-MOSFETs, which in

active state, switch in the ATX 3.3V and 5V outputs into the

3.3VMEM, 3.3VDUAL/3.3VSB and 5VDUAL outputs,

respectively.

5VDL (Pin 15)

Connect this pin to the 5VDUAL output (VOUT5). In either

operating state, the voltage at this pin is provided through a

fully on MOS transistor. This pin is also monitored for under-

voltage events.

5VDLSB (Pin 14)

Connect this pin to the gate of a suitable P-MOSFET or bipolar

PNP. In sleep state, this transistor is switched on, connecting

the ATX 5VSB output to the 5VDUAL regulator output.