874208I Data Sheet

LVDS CLOCK DIVIDER AND FANOUT BUFFER

REVISION A 9/18/14

3

©2014 Integrated Device Technology, Inc.

Function Tables

Input Frequency Divider Operation

The FSEL1 and FSEL0 controls configure the input frequency

divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)

the output frequency is equal to the input frequency (divide-by-1).

The other FSEL[1:0] settings configure the input divider to ÷2, ÷4 or

÷8, respectively.

NOTE: FSEL1, FSEL0 are asynchronous controls

Output Enable Operation

The output enable/disable state of each individual differential output

Qx can be set by the content of the I2C register (see Table 3C). A

logic zero to an I2C bit in register 0 enables the corresponding

differential output, while a logic one disables the differential output

(see Table 3B). After each power cycle, the device resets all I2C bits

(D[7:0]) to its default state (logic 0) and all Qx outputs are enabled.

After the first valid I2C write, the output enable state is controlled by

the I2C register. Setting and changing the output enable state through

the I2C interface is asynchronous to the input reference clock.

I2C Interface Protocol

The ICS874208I uses an I2C slave interface for writing and reading

the device configuration to and from the on-chip configuration

registers. This device uses the standard I2C write format for a write

transaction, and a standard I2C read format for a read transaction.

Figure 1 defines the I2C elements of the standard I2C transaction.

These elements consist of a start bit, data bytes, an acknowledge or

Not-Acknowledge bit and the stop bit. These elements are arranged

to make up the complete I2C transactions as shown in Figure 2 and

Figure 3. Figure 2 is a write transaction while Figure 3 is read

transaction. The 7-bit I2C slave address of the 874208I is a

combination of a 4-bit fixed addresses and two variable bits which are

set by the hardware pins ADR[1:0] (binary 11010, ADR1, ADR0). Bit

0 of slave address is used by the bus controller to select either the

read or write mode. The hardware pins ADR1 and ADR0 should be

individually set by the user to avoid address conflicts of multiple

874208I devices on the same bus.

START (ST) – defined as high-to-low transition on SDA while holding

SCL HIGH.

DATA – between START and STOP cycles, SDA is synchronous with

SCL. Data may change only when SCL is LOW and must be stable

when SCL is HIGH.

ACKNOWLEDGE (AK) – SDA is driven LOW before the SCL rising

edge and held LOW until the SCL falling edge.

STOP (SP) – defined as low-to-high transition on SDA while holding

SCL HIGH

S –

Start or Repeated Start

W –

R/~W is set for Write

R –

R/~W is set for Read

A –Ack

DevAdd –

7 bit Device Address

RegAdd –

8 bit Register Address, MSB = Q7 and LSB = Q0

P –

Stop

Table 3A. FSEL[1:0] Input Selection Function Table

Input

Operation

FSEL1

FSEL0

0 (default)

0 (default)

fQ[7:0] = fREF ÷ 1

01

fQ[7:0] = fREF ÷ 2

10

fQ[7:0] = fREF ÷ 4

11

fQ[7:0] = fREF ÷ 8

Table 3B. Individual Output Enable Control

Bit

Operation

D[7:0]

0 (default)

Output Qx, nQx is enabled.

1

Output Qx, nQx is high-impedance.

Table 3C. Individual output enable control

Bit

D7D6D5D4D3

D2D1D0

Output

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Default

00000

000

Table 3D. I2C Slave Address

76

543

210

1

1

0

1

0

ADR1

ADR0

R/W

Figure 1: Standard I2C Transaction

SW A

A P

DevAdd

Data Byte

SR A

A P

DevAdd

Data Byte

Figure 2: Write Transaction

Figure 3: Read Transaction