ISL6260 datasheet(21/26 Pages) RENESAS

21 / 26 page

FN9162.1

January 3, 2006

Static Mode of Operation - Static Droop using DCR

Sensing

As previously mentioned, the ISL6260 and ISL6260B have

an internal differential amplifier which provides for extremely

accurate voltage regulation at the die of the processor. The

load line regulation is also very accurate, and the process of

selecting the components for the appropriate load line droop

is explained here.

For DCR sensing, the process of compensation for DCR

resistance variation to achieve the desired load line droop

has several steps and is somewhat iterative. Refer to

Figure 42.

In Figure 42 we show a 3 phase solution using DCR

sensing. There are two resistors around the inductor of each

phase. These are labeled RS and RO. These resistors are

used to arrive at the DC voltage drop across each inductor.

Each inductor will have a certain level of DC current flowing

through it, this current when multiplied by the DCR of the

inductor creates a small DC level of voltage. When this

voltage is summed with the other channels DC voltages, the

total DC load current can be derived.

RO is typically 5 to 10

Ω. This resistor is used to tie the

outputs of all channels together and thus create a summed

average of the local CORE voltage output. RS is determined

through an understanding of both the DC and transient load

currents. This value will be covered in the next section.

However, it is important to keep in mind that the output of

each of these RS resistors are tied together to create the

VSUM voltage node. With both the outputs of RO and RS

tied together, the simplified model for the droop circuit can

be derived. This is presented in Figure 43.

Figure 43 shows the simplified model of the droop circuitry.

Essentially one resistor can replace the RO resistors of each

phase and one RS resistor can replace the RS resistors of

each phase. The total DCR drop due to load current can be

replaced by a DC source, the value of which is given by

Equation 5.

where N is the number of channels designed for Active

operation. N = 3 for this example. Another simplification can

be done by reducing the NTC network comprised of Rntc,

Rseries and Rparallel, given in Figure 43, to a single resistor

given as Rn.

The first step in droop load line compensation is to adjust

Rn, ROEQV and RSEQV such that sufficient droop voltage

exists even at light loads between the VSUM and VO’ nodes.

We recognize that these components form a voltage divider.

As a rule of thumb we start with the voltage drop across the

Rn network, VN, to be 0.57 x Vdcr. This ratio provides for a

fairly reasonable amount of light load signal from which to

arrive at droop.

First we calculate the equivalent NTC network resistance,

Rn. Typical values that provide good performance are,

Rseries = 3.57K_1%, Rpar = 4.53K_1% and Rntc = 10k

NTC, ERT-J1VR103J from Panasonic. Rn is then given by

Equation 6.

In our second step we calculate the series resistance from

each phase to the Vsum node, labeled RS1, RS2 and RS3

in Figure 42.

FIGURE 42. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING

bulk

ESR

VSU M

VO '

Vo u t

p h ase1

pha se 2

phas e 3

RS1

RS2

RS 3

RO 3

RO 2

RO1

In te r n a l to

IS L 6 2 6 0

RT N

VSU M

DF B

VO '

VD IF F

VSE N

OC S E T

D R OOP

10 u A

DROO P

VO '

OCS E T

VS UM

IS EN 1

ISEN 2

ISEN 3

IS E N 2

IS E N 1

V dcr

DC R

V dcr

DC R

Vd c r

DC R

ISEN 3

ISEN 2

ISEN 1

V C C_ SE NSE

VSS _ S EN S E

0.01 u F

0.22 u F

To P r oc es sor

S o c k e t K e lv in

Co n n e c tio n s

Ro p n 1

Ro p n 2

to V o u t

Vdcr

EQV

Iout

DCR

-------------------------------

(EQ. 5)

Rseries

Rntc

() Rpar

Rseries

Rntc

Rpar

--------------------------------------------------------------------

3.4k

(EQ. 6)

ISL6260, ISL6260B

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