HMP8170

FN4284 Rev 6.00

Page 21 of 33

Sep 2003

TABLE 38. START V_BLANK HIGH REGISTER

SUB ADDRESS = 24H

BIT

NUMBER

FUNCTION

DESCRIPTION

RESET

STATE

7-1

Reserved

0000000B

0

MSB Assert BLANK

Output Signal

(Vertical)

This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit

start_vertical_blank register. This register is ignored unless BLANK is configured as an output.

1B

TABLE 39. END V_BLANK REGISTER

SUB ADDRESS = 25H

BIT

NUMBER

FUNCTION

DESCRIPTION

RESET

STATE

7-0

Negate BLANK

Output Signal

(Vertical)

During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel

input data (and what line number to start generating active output video) each odd field; for

even fields, it occurs on line (n + 262) or (n + 313).

The leading edge of VSYNC at the start of an odd field is count 000H (note that this does not

follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is

configured as an output.

13H

TABLE 40. FIELD CONTROL REGISTER 1

SUB ADDRESS = 26H

BIT

NUMBER

FUNCTION

DESCRIPTION

RESET

STATE

7-0

Field Detect

Window Size Low

This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect

Window Size value. The value specifies the number of 1x clock cycles in the detection window

before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge

of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the

FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured

as inputs.

80H

TABLE 41. FIELD CONTROL REGISTER 2

SUB ADDRESS = 27H

BIT

NUMBER

FUNCTION

DESCRIPTION

RESET

STATE

7-4

Half Line Count

Reset Value

These bits specify the value to load to the vertical half line counter when the selected edge of

VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.

00000B

2

VSYNC Edge

Select

This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine

the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are

configured as inputs.

0 = leading edge

1 = trailing edge

0B

1

FIELD Detect

Select

This bit specifies whether an odd or even field is starting when the leading edge of HSYNC

occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are

configured as inputs.

0 = odd field

1 = even field

0B

0

Field Detect

Window Size High

This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window

Size value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.

0B