M66592FP datasheet(21/129 Pages) RENESAS

21 / 129 page

M66592F P/W G

Rev 1.00 2004.10.01 page 19 of 125

System configuration status register [SYSSTS]

<Address: 02H>

LNST

Bit

Name

Function

S/W

H/W

Note

15-2 Nothing is placed here. These should be fixed at “0”.

1-0 LNST

USB data line status

Please see the detailed explanation concerning

this item.

2.3.2

Notes»

None in particular

2.3.1

USB block operation enabled

The USBE bit of the SYSCFG register should be used to enable USB block operation.

The same bit can be used to carry out an S/W reset of the controller. When software is set to “USBE=0”, the

controller resets the register targeted for S/W reset initialization to the default setting value. As long as “USBE=0” is

set, no data can be written by software to the bit targeted for S/W reset initialization. “USBE=1” should be set

following an S/W reset to enable controller operation.

2.3.2

Line status monitor

Table 2.3 shows the USB data bus line statuses of the controller. The controller monitors the line status (D+ line

and D- line) of the USB data bus using the LNST bit of the SYSSTS register. The LNST bit is configured of two bits.

For the meaning of each of the bits, please refer to the table below. The timing at which the LNST bit becomes valid

differs depending on the selected controller function. In the normal operating state, the line status can be monitored

on an ongoing basis, but in the low-power sleep state, the line status cannot be monitored.

Table 2.3 USB data bus line statuses

LNST [1]

LNST [0]

During Full-Speed

operation

During Hi-Speed operation

During chirp operation

SE0

Squelch

J State

not Squelch

Chirp J

K State

Invalid

Chirp K

SE1

Invalid

Chirp:

The reset handshake protocol is being executed in the Hi-Speed operation enabled state (HSE = “1”).

Squelch:

SE0 or Idle state

not Squelch: Hi-Speed J state or Hi-Speed K state

Chirp J:

Chirp J state

Chirp K:

Chirp K state

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