ADF4002BCPZ datasheet(3/24 Pages) AD

3 / 24 page

ADF4002

Rev. 0 | Page 3 of 24

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,

TA = TMAX to TMIN, unless otherwise noted.

Table 1.

B Version1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RF CHARACTERISTICS

See Figure 12 for input circuit

RF Input Sensitivity

−10

dBm

RF Input Frequency (RFIN)

400

MHz

For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs

REFIN CHARACTERISTICS

REFIN Input Frequency

300

MHz

For REFIN < 20 MHz, ensure SR > 50 V/μs

REFIN Input Sensitivity2

0.8

VDD

V p-p

Biased at AVDD/23

REFIN Input Capacitance

REFIN Input Current

±100

μA

PHASE DETECTOR

Phase Detector Frequency4

200

MHz

CHARGE PUMP

Programmable, see Figure 19

ICP Sink/Source

High Value

With RSET = 5.1 kΩ

Low Value

625

μA

Absolute Accuracy

2.5

With RSET = 5.1 kΩ

RSET Range

3.0

kΩ

See Figure 19

ICP Three-State Leakage

TA = 25°C

ICP vs. VCP

1.5

0.5 V ≤ VCP ≤ VP – 0.5 V

Sink and Source Current Matching

0.5 V ≤ VCP ≤ VP – 0.5 V

ICP vs. Temperature

VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage

1.4

VIL, Input Low Voltage

0.6

IINH, IINL, Input Current

±1

μA

CIN, Input Capacitance

LOGIC OUTPUTS

VOH, Output High Voltage

1.4

Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V

VOH, Output High Voltage

VDD – 0.4

CMOS output chosen

IOH

100

μA

VOL, Output Low Voltage

0.4

IOL = 500 μA

POWER SUPPLIES

AVDD

2.7

3.3

DVDD

AVDD

5.5

AVDD ≤ VP ≤ 5.5 V

IDD5 (AIDD

+ DI )

5.0

6.0

0.4

TA = 25°C

Power-Down Mode

μA

AIDD + DIDD

NOISE CHARACTERISTICS

Normalized Phase Noise Floor6

–222

dBc/Hz

1 Operating temperature range (B version) is –40°C to +85°C.

2 AVDD = DVDD = 3 V.

3 AC coupling ensures AVDD/2 bias.

4 Guaranteed by design. Sample tested to ensure compliance. Use of the PFD at frequencies above 104 MHz requires the minimum antibacklash pulse width enabled.

5 TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN

frequency in MHz.

6 The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)

and 10logFPFD. PNSYNTH = PNTOT – 10logFPFD – 20logN. All phase noise measurements were performed with an Agilent E5500 phase noise test system, using the EVAL-

ADF4002EB1 and the HP8644B as the PLL reference.

ADF4002BCPZ Datasheet(PDF) 3 Page - Analog Devices

ADF4002BCPZ Datasheet(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL