ISL73840SEHFSLASHPROTO datasheet(4/24 Pages) RENESAS

4 / 24 page

ISL73840SEH

FN8845 Rev.3.00

Page 4 of 24

Feb 23, 2018

FIGURE 3. ESD Circuits

Pin Configuration

ISL73840SEH

(28 LD CDFP)

TOP VIEW

V+

IN16

IN15

IN14

IN13

IN12

IN11

IN10

IN09

GND

VREF

VOUT

V-

IN08

IN07

IN06

IN05

IN04

IN03

IN02

IN01

Pin Descriptions

PIN NAME

PIN NUMBER

DESCRIPTION

VOUT

Output for multiplexer (see Circuit 1 in Figure 3)

V+

Positive power supply (see Circuit 3 in Figure 3)

V-

Negative power supply (see Circuit 4 in Figure 3)

2, 3

Not electrically connected

INx

4, 5, 6, 7, 8, 9, 10, 11, 19, 20, 21,

22, 23, 24, 25, 26

Input for multiplexer (see Circuit 2 in Figure 3)

14, 15, 16, 17

Address lines for multiplexer (see Circuit 3 in Figure 3)

Enable control for multiplexer (active low, see Circuit 3 in Figure 3)

VREF

Reference voltage used to set logic thresholds (see Circuit 3 in Figure 3)

GND

Ground

LID

Package Lid is internally connected to GND (Pin 12)

±20V

20V

±40V

20V

V+

V-

GND

Circuit 1

Circuit 2

Circuit 3

Circuit 4

20V

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