ISL97673 datasheet(21/28 Pages) RENESAS

21 / 28 page

ISL97673

FN7633 Rev.3.00

Page 21 of 28

Sep 19, 2017

This register has two bits that control either SMBus/I2C

controlled or external PWM controlled PWM dimming and

a single bit that controls the BL ON/OFF state. The

remaining bits are reserved. The bit assignment is shown

in Figure 30. All other bits in the Device Control Register

will read as low unless otherwise written.

• All defined control bits return their current, latched

value when read.

A value of 1 written to BL_CTL turns on the BL in 4ms or

less after the write cycle completes. The BL is

• deemed to be on when Bit 3 BL_STAT of Register 0x02

is 1 and Register 0x09 is not 0.

• A value of 0 written to BL_CTL immediately turns off the

BL. The BL is deemed to be off when Bit 3 BL_STAT of

• When SMBus/I2C mode with DPST is selected,

from SMBus/I2C.

• The default value for Register 0x01 is 0x00.

Fault/Status Register (0x02)

This register has 6 status bits that allow monitoring of

the backlight controller’s operating state. Bit 0 is a logical

“OR” of all fault codes to simplify error detection. Not all

of the bits in this register are fault related (Bit 3 is a

simple BL status indicator). The remaining bits are

reserved and return a “0” when read. All of the bits in

this register are read-only, with the exception of Bit 0,

which can be cleared by writing to it.

• A Read Byte cycle to Register 0x02 indicates the

current BL on/off status in BL_STAT (1 if the BL is on,

0 if the BL is off).

• A Read Byte cycles to Register 0x2 also returns

FAULT as the logical OR of THRM_SHDN, OV_CURR,

2_CH_SD, and 1_CH_SD should these events occur.

• 1_CH_SD returns a 1 if one or more channels have

faulted out.

• 2_CH_SD returns a 1 if two or more channels have

faulted out.

• A fault will not be reported in the event that the BL is

commanded on and then immediately off by the

system.

• When FAULT is set to 1, it will remain at 1 even if the

signal which sets it goes away. FAULT will be cleared

when the BL_CTL bit of the Device Control Register is

toggled or when written low. At that time, if the fault

condition is still present or reoccurs, FAULT will be

set to 1 again. BL_STAT will not cause FAULT to be

set

• The default value for Register 0x02 is 0x00.

Si Revision Register (0x03)

The Si Revision register has 3 bits that allows up to 8

silicon revisions each. In order to keep the number of

silicon revisions low, the revision field will not be updated

unless the part will make it out to the user’s factory.

Thus, if during the first silicon engineering development

process, 2 silicon spins were needed, the revision

remains as 0. All of the bits in this register are read-only.

• The default value for Register 0x03 is 0xC8.

The initial value of REV shall be 0. Subsequent values of

REV will increment by 1.

FAULT/STATUS REGISTER

RESERVED RESERVED 2_CH_SD 1_CH_SD

BL_STAT OV_CURR THRM_SHDN

FAULT

Bit 7 (R)

Bit 6 (R)

Bit 5 (R)

Bit 4 (R)

Bit 3 (R)

Bit 2 (R)

Bit 1 (R)

Bit 0 (R)

BIT

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

Bit 5

2_CH_SD

= Two LED output channels are shutdown (1 = shutdown, 0 = OK)

Bit 4

1_CH_SD

= One LED output channel is shutdown (1 = shutdown, 0 = OK)

Bit 3

BL_STAT

= BL Status (1 = BL On, 0 = BL Off)

Bit 2

OV_CURR

= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)

Bit 1

THRM_SHDN

= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)

Bit 0

FAULT

= Fault occurred (Logic “OR” of all of the fault conditions)

FIGURE 31. DESCRIPTIONS OF FAULT/STATUS REGISTER

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