AD12401

Rev. A | Page 9 of 28

Table 7. Output Coding (Twos Complement)

Code

KWS

JWS

Digital Output

4095

+1.6

+0.8

0111 1111 1111

.

.

.

.

.

.

.

.

.

.

.

.

2048

0

0

0000 0000 0000

2047

−0.000781 to

+0.0003905

1111 1111 1111

.

.

.

.

.

.

.

.

0

−1.6 to

+0.8

1000 0000 0000

Table 8. Option Pin List with Necessary Associated Circuitry

Pin

Name

Active

High

Logic

Level

Type

Default

Level

Associated Circuitry

Within Part

RESET

Low

LVTTL

High

3.74 kΩ Pull-Up

DR_EN

High

LVTTL

High

Weak Pull-Up (>16 kΩ)

ENCODE

100

Ω

100

Ω

100

Ω

100

Ω

3.3V

3.3V

PECL

DRIVER

ENCODE

Figure 2. ENCODE Equivalent Circuit

ENC

400MHZ

DRA

DRB

DRB

DRA

DATA OUT B

DR_EN

DATA OUT A

N – 74

N– 1

N – 73

N

N

N + 2

N + 1

N + 1

N + 2

N + 3

N + 3

N + 5

N + 7

N + 4

N + 6

N + 8

1

1

74 CLOCK CYCLES

1. DATA LOST DUE TO ASSERTION OF DR_EN. LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID.

2. IF A SINGLE-ENDED SINE WAVE IS USED FOR ENCODE, USE THE ZERO CROSSING POINT (AC-COUPLED) AS

THE 50% POINT AND APPLY THE SAME TIMING INFORMATION.

3. THE DR_EN PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES.

THE DR_EN PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12401. IF APPLIED

ASYNCHRONOUSLY, DR_EN MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION.

THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE DR_EN PIN IS SET HIGH AGAIN. DRA AND DRB RESUME

ON THE NEXT VALID DRA AFTER DR_EN IS RETURNED HIGH. IF THIS FEATURE IS NOT REQUIRED, TIE THIS

PIN TO 3.3V THROUGH A 3.74k

Ω RESISTOR OR LEAVE IT FLOATING.

NOTES

Figure 3. Timing Diagram

ENC

DATA OUT

DR

ENC

DR

Figure 4. Highlighted Timing Diagram