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MPC604E9QEC/D Datasheet(PDF) 13 Page - NXP Semiconductors |
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MPC604E9QEC/D Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 29 page ![]() PID9q-604e Hardware Specifications 13 PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Figure 4 provides the output timing diagram for the 604e. Figure 4. Output Timing Diagram 1.4.3 JTAG AC Timing SpeciÞcations Table 9 provides the JTAG AC timing speciÞcations. Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3 ± 5%, GND = 0 V dc, CL = 5 pF, 0 £ Tj £ 105 ¡C Num Characteristic Min Max Unit Notes TCK frequency of operation 0 16 MHz 1 TCK cycle time 62.5 Ñ ns 2 TCK clock pulse width measured at 0.9 V 25 Ñ ns 3 TCK rise and fall times 0 3 ns 4 TRST setup time to TCK rising edge 13 Ñ ns 1 5 TRST assert time 40 Ñ ns 6 Boundary-scan input data setup time 0 Ñ ns 2 7 Boundary-scan input data hold time 27 Ñ ns 2 SYSCLK 11 13 12 14 15 16 ALL OUTPUTS (Except TS, ABB, DBB, TS, XATS ARTRY, SHD ABB, DBB VM VM VM = Midpoint Voltage ( 0.9 V) ARTRY, XATS, SHD) 14 VM 12 20 18 17 21 19 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com AR CH IVE D B Y F RE ES CA LE SE MI CO ND UC TO R, INC . |
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