L6382D datasheet(10/14 Pages) STMICROELECTRONICS

10 / 14 page

L6382D

10/14

BLOCK DESCRIPTION

5.1 SUPPLY SECTION

■ PUVLO ( Power Under Voltage Lock Out): This block controls the power management of the L6382D

ensuring the right current consumption in each operating state, the correct VREF current capability, the

driver enabling and the high-voltage start-up generator switching.

During Start-up the device sinks the current necessary to charge the external capacitor on pin VCC from

the high voltage bus; in this state the other IC's functions are disabled and the current consumption of

the whole IC is less than 150

µA.

When the voltage on VCC pin reaches VccON, the IC enters the save mode where the

µPUVLO block

controls Vcc between VccON and VccSM by switching ON/OFF the high voltage start-up generator.

■ HVSU (High-Voltage Start-Up generator): a 600V internal MOS transistor structure controls the Vcc

supply voltage during

start-up and save mode conditions and it reduces the power losses during

operating Mode by switching OFF the MOS transistor. The transistor has a source current capability of

up to 30mA.

■ TPR (Two Point Regulator) & PWS: during operating mode, the TPR block controls the PSW switch

in order to regulate the IC supply voltage (VCC) to a value in the range between TPR(ON) and

TPR(OFF) by switching ON and OFF the PSW transistor.

– Vcc > TPRst: the PSW is switched ON immediately;

– TPR(ON) < Vcc < TPRst: the PSW is switched ON at the following falling edge of LGI;

– Vcc < TPR(OFF): the PSW is switched OFF at the following falling edge on LGI.

When the PSW switch is OFF, the diodes build a charge pump structure so that, connecting the TPR pin

to a switching voltage (through a capacitor) it is possible to supply the low voltage section of the chip with-

out adding any further external component. The diodes and the switch are designed to withstand a peak

current of at least 200mARMS.

5.2 3.3V REFERENCE VOLTAGE

This block is used to supply the microcontroller; this source is able to supply 10mA in

save mode and

30mA in

operating mode; moreover, during start-up when VREF is not yet available, an additional circuit is

ensures that, even sinking 3mA, the pin voltage doesn't exceed 1.2V.

The reference is available until Vcc is above VREF(OFF); below that it turns off and the additional sinking

circuit is enabled again.

5.3 DRIVERS

■ LSD (Low Side Driver): it consists of a level shifter from 3.3V logic signal (LGI) to Vcc MOS driving level;

conceived for the half-bridge low-side power MOS, it is able to source and sink 120mA (min).

■ HSD (Level Shifter and High Side Driver): it consists of a level shifter from 3.3V logic signal (HGI) to the

high side gate driver input up to 600V. Conceived for the half-bridge high-side power MOS, the HSD is

able to source 120mA from HSB to HSG (turn-on) and to sink 120mA to HSS (turn-off).

■ PFD (Power Factor Driver): it consists of a level shifter from 3.3V logic signal (PFI) to Vcc MOS driving

level: the driver is able to source 120mA from Vcc to PFG (turn-on) and to sink 250mA to GND (turn-

off); it is suitable to drive the MOS of the PFC pre-regulator stage.

■ HED (Heat Driver): it consists of a level shifter from 3.3V logic signal (HEI) to Vcc MOS driving level;

the driver is able to source 30mA from Vcc to HEG and to sink 75mA to GND and it is suitable for the

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