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CS4811 Datasheet(PDF) 5 Page - Applied Micro Circuits Corporation |
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CS4811 Datasheet(HTML) 5 Page - Applied Micro Circuits Corporation |
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5 / 5 page ![]() Empowering Intelligent Optical Networks 5 Empowering Intelligent Optical Networks 5 AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’s Term and Con- ditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2004 Applied Micro Circuits Corporation. 215 Moffett Park Drive, Sunnyvale, CA 94089• Tel: 408-542-8600 • Fax: 408-542-8601 • http://www.amcc.com for technical support, please call 800 840-6055 or email support@amcc.com FINAL Product Brief TIGRIS OC-48 Multi Protocol Termination for 2047 Channels Part Number S4811, Rev. 2.4 July 2006 External Memory Support • Industry standard DDR333 SDRAM support. • Separate 64b DRAM memory banks for Transmit and Receive frame storage. • Supports 256Mb, 512Mb, and 1Gb DRAM technology. • Supports x16 discrete. Sub Rate DS3 Support • Subrate Services supported for all 48 DS3 payloads. • Interoperates with the following subrate DS3 protocols: • Quick Eagle (formerly Digital Link) • ADC/Kentrox • Larscom •Adtran • Verilink Loopbacks • Wire Level FTI loopback. • DS0 loopback on FTI interfaces. • Packet level loopbacks per channel for packets received/ transmitted on FTI, ATI, and SPI interfaces. • All packet level loopbacks occur at internal queueing points in the on chip MMU (Memory Management Unit). External CPU Interface • General purpose 16-bit microprocessor interface for device initialization, control and monitoring. The interface supports both Intel and Motorola type microprocessors. • Supports processor-based packet/cell injection and retrieval to/from the line interface as well as to/from the system interface. • Operation up to 66 Mhz. • Maskable interrupt support for errors and statistics counter threshold events. |
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