LPC86X datasheet(39/99 Pages) NXP

39 / 99 page

LPC86x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev.3 — 28 April 2023

39 of 97

NXP Semiconductors

LPC86x

32-bit Arm Cortex-M0+ microcontroller

8.25 System control

8.25.1 Reset

Reset has four sources on the LPC86x: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the FRO and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

In deep power-down mode, an external pull-up resistor is required on the RESET pin.

8.25.2 Brownout detection

The LPC86x includes up to four levels for monitoring the voltage on the VDD pin. If this

voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

to cause a CPU interrupt. Alternatively, the software can monitor the signal by reading a

dedicated status register. Four threshold levels can be selected to cause a forced reset of

the chip. BOD is enabled by default and reset level 0 is default.

Fig 12. Reset pad configuration

VSS

reset

aaa-004613

VDD

Rpu

ESD

20 ns RC

GLITCH FILTER

LPC86X Datasheet(PDF) 39 Page - NXP Semiconductors