ADV212 datasheet(21/44 Pages) AD

21 / 44 page

ADV212

Rev. 0 | Page 21 of 44

Table 16. Pin Function Descriptions

121-Ball Package

144-Ball Package

Pin No.

Location

Pin No.

Location

Mnemonic

Pins

Used

Type

Description

119

132

L12

MCLK

System Input Clock. See the PLL section.

117

131

L11

RESET

Reset. Causes the ADV212 to immediately reset.

CS, RD, WE, DACK0, DACK1, DREQ0, and DREQ1

must be held high when a RESET is applied.

37 to 34,

27 to 25,

16, 15, 24,

14 to 12,

2, 6, 5

D4 to D1,

C5 to C3,

B5, B4, C2,

B3 to B1,

A2, A6, A5

64, 49 to 51,

37 to 39, 25

to 27, 13 to

15, 2 to 4

F4, E1 to E3,

D1 to D3,

C1 to C3,

B1 to B3,

A2 to A4

HDATA

[15:0]

I/O

Host Data Bus. With HDATA [23:16],

HDATA [27:24], and HDATA [31:28], these pins

make up the 32-bit wide host data bus. The

async host interface is interfaced together

with ADDR[3:0], CS, WE, RD, and ACK.

Unused HDATA pins should be pulled down

via a 10 kΩ resistor.

88, 107,

87, 97

H11, K8,

H10, J9

108 to 106,

J12, J11,

J10, H12

ADDR [3:0]

Address Bus for the Host Interface.

H11

Chip Select. This signal is used to qualify

addressed read and write access to the

ADV212 using the host interface.

H10

WE1

Write Enable Used with the Host Interface.

RDFB2

Read Enable When Fly-By DMA Is Enabled.

Simultaneous assertion of WE and DACK low

activates the HDATA bus, even if the DMA

channels are disabled.

G12

RD1

Read Enable Used with the Host Interface.

WEFB3

Write Enable When Fly-By DMA Is Enabled.

Simultaneous assertion of RD and DACK low

activates the HDATA bus, even if the DMA

channels are disabled.

G11

ACK

Acknowledge. Used for direct register accesses.

This signal indicates that the last register access

was successful. Due to synchronization issues,

control and status register accesses might incur

an additional delay; therefore, the host software

should wait for acknowledgment from the

ADV212 before attempting another register

access.

Accesses to the FIFOs (external DMA modes),

on the other hand, are guaranteed to occur

immediately, provided that space is available;

therefore, the host software does not need to

wait for ACK before attempting another register

access, provided that the timing constraints

are observed.

If ACK is shared with more than one device, ACK

should be connected to a pull-up resistor (10 kΩ)

and the PLL_HI register, Bit 4, must be set to 1.

G10

IRQ

Interrupt. This pin indicates that the ADV212

requires the attention of the host processor.

This pin can be programmed to indicate the

status of the internal interrupt conditions

within the ADV212. The interrupt sources are

enabled via the bits in register EIRQIE.

ADV212 Datasheet(PDF) 21 Page - Analog Devices

ADV212 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL