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ST72361 Datasheet(PDF) 211 Page - STMicroelectronics |
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ST72361 Datasheet(HTML) 211 Page - STMicroelectronics |
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211 / 224 page ![]() ST72361 211/224 FLASH OPTION BYTES (Cont’d) OPT2:1 = PKG[1:0] Package selection These option bits select the device package. Note: Pads that are not bonded to external pins are in input pull-up configuration when the pack- age selection option bits have been properly pro- grammed. The configuration of these pads must be kept in reset state to avoid added current con- sumption. OPT0 = FMP_R Flash memory read-out protec- tion Read-out protection, when selected provides a protection against program memory content ex- traction and against write access to Flash memo- ry. Erasing the option bytes when the FMP_R op- tion is selected causes the whole user memory to be erased first, and the device can be repro- grammed. Refer to Section 4.3.1 and the ST7 Flash Programming Reference Manual for more details. 0: Read-out protection enabled 1: Read-out protection disabled OPTION BYTE 1 OPT7:6 = AFI_MAP[1:0] AFI Mapping These option bits allow the mapping of some of the Alternate Functions to be changed. OPT5:4 = OSCTYPE[1:0] Oscillator Type These option bits select the ST7 main clock source type. OPT3:2 = OSCRANGE[1:0] Oscillator range If the resonator oscillator type is selected, these option bits select the resonator oscillator. This se- lection corresponds to the frequency range of the resonator used. If external source is selected with the OSCTYPE option, then the OSCRANGE op- tion must be selected with the corresponding range. OPT1 = Reserved OPT0 = RSTC RESET clock cycle selection This option bit selects the number of CPU cycles inserted during the RESET phase and when exit- ing HALT mode. For resonator oscillators, it is ad- vised to select 4096 due to the long crystal stabili- zation time. 0: Reset phase with 4096 CPU cycles 1: Reset phase with 256 CPU cycles Selected Package PKG 1 0 LQFP 64 1 x LQFP 44 0 1 LQFP 32 0 0 AFI Mapping 1 AFI_MAP(1) T16_OCMP1 on PD3 T16_OCMP2 on PD5 T16_ICAP1 on PD4 LINSCI2_SCK not available LINSCI2_TDO not available LINSCI2_RDI not available 0 T16_OCMP1 on PB6 T16_OCMP2 on PB7 T16_ICAP1 on PC0 LINSCI2_SCK on PD3 LINSCI2_TDO on PD5 LINSCI2_RDI on PD4 1 AFI Mapping 0 AFI_MAP(0) T16_ICAP2 is mapped on PD1 0 T16_ICAP2 is mapped on PC1 1 Clock Source OSCTYPE 1 0 Resonator Oscillator 0 0 Reserved 0 1 Reserved internal clock source (used only in ICC mode) 1 0 External Source 1 1 Typ. Freq. Range OSCRANGE 1 0 LP 1~2 MHz 0 0 MP 2~4 MHz 0 1 MS 4~8 MHz 1 0 HS 8~16 MHz 1 1 |
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