ST72361 datasheet(222/224 Pages) STMICROELECTRONICS

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ST72361

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IMPORTANT NOTES (Cont’d)

Occurrence

The occurrence of the problem is random and pro-

portional to the baud rate. With a transmit frequen-

19200

baud

(fCPU = 8

MHz

and

SCIBRR = 0xC9), the wrong break duration occur-

rence is around 1%.

Analysis

The LIN protocol specifies a minimum of 13 bits for

the break duration, but there is no maximum value.

Nevertheless, the maximum length of the header

is specified as (14+10+10+1) x 1.4 = 49 bits. This

is composed of:

- the synch break field (14 bits)

- the synch field (10 bits)

- the identifier field (10 bits)

Every LIN frame starts with a break character.

Adding an idle character increases the length of

each header by 10 bits. When the problem occurs,

the header length is increased by 11 bits and be-

comes ((14+11)+10+10+1) = 45 bits.

To conclude, the problem is not always critical for

LIN communication if the software keeps the time

between the sync field and the ID smaller than 4

bits, that is, 208µs at 19200 baud.

The workaround is the same as for SCI mode but

considering the low probability of occurrence (1%),

it may be better to keep the break generation se-

quence as it is.

16.2.2 16-bit and 8-bit Timer PWM Mode

In PWM mode, the first PWM pulse is missed after

writing the value FFFCh in the OC1R or OC2R

16.3 ROM DEVICES ONLY

16.3.1 16-bit Timer PWM Mode Buffering

Feature Change

In all devices, the frequency and period of the

PWM signal are controlled by comparing the coun-

ter with a 16-bit buffer updated by the OCiHR and

OCiLR registers. In ROM devices, contrary to the

description in Section 10.5.3.5 on page 102, the

output compare function is not inhibited after a

write instruction to the OCiHR register. Instead the

buffer update at the end of the PWM period is in-

hibited until OCiLR is written. This improved buffer

handling is fully compatible with applications writ-

ten for Flash devices.

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