6.42

21

70V35/34S/L (70V25/24S/L)

High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V35/34 (IDT70V25/24) SRAMs.

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70V35/34 (IDT70V25/24) SRAM in

master mode, are push-pull type outputs and do not require pull up

resistorstooperate.IftheseSRAMsarebeingexpandedindepth,then

theBUSYindicationfortheresultingarrayrequirestheuseofanexternal

AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70V35/34 (IDT70V25/24) SRAM array in

widthwhileusingBUSYlogic,onemasterpartisusedtodecidewhichside

of the SRAM array will receive a BUSY indication, and to output that

indication. Any number of slaves to be addressed in the same address

range as the master, use the BUSY signal as a write inhibit signal. Thus

on the IDT70V35/34 (IDT70V25/24) SRAM the BUSYpin is an output if

thepartisusedasamaster(M/Spin=VIH),andtheBUSYpinisaninput

if the part used as a slave (M/S pin = VIL) as shown in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

The BUSYarbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupted data in the slave.

Semaphores

The IDT70V35/34 (IDT70V25/24) is an extremely fast Dual-Port 8/

4K x 18 (8/4K x 16) CMOS Static RAM with an additional 8 address

locationsdedicatedtobinarysemaphoreflags.Theseflagsalloweither

processorontheleftorrightsideoftheDual-PortSRAMtoclaimaprivilege

overtheotherprocessorforfunctionsdefinedbythesystemdesigner’s

Functional Description

The IDT70V35/34 (IDT70V25/24) provides two ports with separate

control,addressandI/Opinsthatpermitindependentaccessforreadsor

writestoanylocationinmemory.TheIDT70V35/34(IDT70V25/24)has

anautomaticpowerdownfeaturecontrolledbyCE.TheCEcontrolson-

chip power down circuitry that permits the respective port to go into a

standby mode when not selected (CE HIGH). When a port is enabled,

accesstotheentirememoryarrayispermitted.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 1FFE

(HEX) (FFE for IDT70V34 and IDT70V24), where a write is defined as

theCER=R/WR=VILperTruthTableIII.Theleftportclearstheinterrupt

on the IDT70V35 and IDT70V25 by an address location 1FFE (FFE for

IDT70V34andIDT70V24)accesswhenCEL=OEL=VIL,R/WLisa"don't

care".Likewise,therightportinterruptflag(INTR)issetwhentheleftport

writestomemorylocation1FFFforIDT70V35andIDT70V25(HEX)(FFF

for IDT70V34 and IDT70V24) and to clear the interrupt flag (INTR), the

right port must read the memory location 1FFF for IDT70V35 and

IDT70V25 (FFF for IDT70V34 and IDT70V24). The message (16 bits)

at 1FFE or 1FFF for IDT70V35 and IDT70V25 (FFE or FFF for

IDT70V34 and IDT70V24) is user-defined, since it is an addressable

SRAMlocation.Iftheinterruptfunctionisnotused,addresslocations1FFE

and1FFFforIDT70V35andIDT70V25(FFEandFFFforIDT70V34and

IDT70V24)arenotusedasmailboxes,butaspartoftherandomaccess

memory. Refer to Truth Table III for the interrupt operation.

Busy Logic

BusyLogicprovidesahardwareindicationthatbothportsoftheSRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheSRAMis“busy”.

TheBUSY pincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

to prevent the write from proceeding.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

5624 drw 19

MASTER

Dual Port

SRAM

BUSYL

BUSYR

CE

MASTER

Dual Port

SRAM

BUSYL

BUSYR

CE

SLAVE

Dual Port

SRAM

BUSYL

BUSYR

CE

SLAVE

Dual Port

SRAM

BUSYL

BUSYR

CE

BUSYL

BUSYR