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CYT3DLABAS Datasheet(PDF) 39 Page - Infineon Technologies AG |
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CYT3DLABAS Datasheet(HTML) 39 Page - Infineon Technologies AG |
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39 / 207 page  P18.3 C2 5 HSIO_STDLN P18.4 D1 8 HSIO_STDLN P18.5 D2 9 HSIO_STDLN P18.6 E1 10 HSIO_STDLN P18.7 E2 11 HSIO_STDLN P19.0 C3 14 HSIO_STDLN P19.1 D3 15 HSIO_STDLN P19.2 E3 16 HSIO_STDLN P19.3 E4 17 HSIO_STDLN P20.0 F1 24 HSIO_STDLN P20.1 F2 25 HSIO_STDLN P20.2 G1 26 HSIO_STDLN P20.3 G2 27 HSIO_STDLN P20.4 H1 30 HSIO_STDLN P20.5 H2 31 HSIO_STDLN P20.6 J1 32 HSIO_STDLN P20.7 J2 33 HSIO_STDLN P21.0 G3 36 HSIO_STDLN P21.1 H3 37 HSIO_STDLN P21.2 J3 38 HSIO_STDLN P21.3 H4 39 HSIO_STDLN FPD0_TAP T12 90 FPD0_TAN U12 91 FPD0_TBP V13 94 FPD0_TBN V14 95 FPD0_TCLKP R13 98 FPD0_TCLKN R14 99 FPD0_TCP T15 102 FPD0_TCN U15 103 FPD0_TDP V16 106 FPD0_TDN V17 107 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (continued) Name Package I/O Type DeepSleep Mapping Analog/HV SMARTIO 272-BGA 216-TEQFP HCon#0 HCon#29[23] HCon#30 Pin Pin DS #5[24, 25] DS #6 |
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