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CYT4DNJBJS Datasheet(PDF) 24 Page - Infineon Technologies AG

Part # CYT4DNJBJS
Description  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
PDF  209 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

CYT4DNJBJS Datasheet(HTML) 24 Page - Infineon Technologies AG

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Datasheet
24
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Flash base address map
5
Flash base address map
Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions
along with their respective base addresses.
Table 5-1
Code-flash address mapping in single bank mode
Code-flash Size (KB) Large Sectors
(LS)
Small Sectors
(SS)
Large Sector Base Address
Small Sector Base Address
6336
32 KB × 190
8 KB × 32
0x1000 0000
0x105F 0000
Table 5-2
Work-flash address mapping in single bank mode
Work-flash Size
(KB)
Large Sectors
Small Sectors
Large Sector Base Address
Small Sector Base Address
128
2 KB × 48
128 B × 256
0x1400 0000
0x1401 8000
Table 5-3
Code-flash address mapping in dual bank mode (Mapping A)
Code-flash
Size (KB)
First Half
LS
First Half
SS
Second
Half LS
Second
Half SS
First Half
LS Base
Address
First Half
SS Base
Address
Second Half
LS Base
Address
Second
Half SS
Base
Address
6336
32 KB × 95
8 KB × 16
32 KB × 95
8 KB × 16 0x1000 0000 0x102F 8000 0x1200 0000 0x122F 8000
Table 5-4
Code-flash address mapping in dual bank mode (Mapping B)
Code-flash
Size (KB)
First
Half LS
First
Half SS
Second
Half LS
Second
Half SS
First Half
LS Base
Address
First Half
SS Base
Address
Second
Half
LS Base
Address
Second
Half SS
Base
Address
6336
32 KB × 95
8 KB × 16
32 KB × 95
8 KB × 16 0x1200 0000 0x122F 8000 0x1000 0000 0x102F 8000
Table 5-5
Work-flash address mapping in dual bank mode (Mapping A)
Work-flash
Size (KB)
First
Half LS
First
Half SS
Second
Half LS
Second
Half SS
First Half
LS Base
Address
First Half
SS Base
Address
Second
Half
LS Base
Address
Second
Half SS
Base
Address
128
2 KB × 24
128 B × 128
2 KB × 24
128 B × 128 0x1400 0000 0x1400 C000 0x1500 0000 0x1500 C000
Table 5-6
Work-flash address mapping in dual bank mode (Mapping B)
Work-flash
Size (KB)
First
Half LS
First
Half SS
Second
Half LS
Second
Half SS
First Half
LS Base
Address
First Half
SS Base
Address
Second
Half
LS Base
Address
Second
Half SS
Base
Address
128
2 KB × 24
128 B × 128
2 KB × 24
128 B × 128 0x1500 0000 0x1500 C000 0x1400 0000 0x1401 8000



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