82V3012PVG datasheet(13/33 Pages) RENESAS

13 / 33 page

Functional Description

February 6, 2009

IDT82V3012

T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

Figure - 5 Reference Switch with TIE Control Block Enabled

Figure - 6 Reference Switch with TIE Control Block Disabled

2.7

DPLL BLOCK

As shown in Figure - 7, the DPLL Block consists of a Phase Detector,

a Limiter, a Loop Filter, a Digital Control Oscillator and Divider.

2.7.1

PHASE DETECTOR (PHD)

In the Normal mode, the Phase Detector compares the virtual

reference signal from the TIE Control Circuit with the feedback signal

from the Frequency Select Circuit, and outputs an error signal

corresponding to the phase difference. This error signal is sent to the

Limiter circuit for phase slope control.

In the Freerun or Holdover mode, the Frequency Select Circuit, the

Phase Detector and the Limiter are inactive, and the input reference

signal is not used.

2.7.2

LIMITER

The Limiter is used to limit the phase slope. It ensures that the

maximum output phase slope is limited to 5 ns per 125 µs for all input

transient conditions. This well meets the AT&T TR62411 and Telcordia

GR-1244-CORE specifications, which specify the maximum phase slope

of 7.6 ns per 125 µs and 81 ns per 1.326 ms respectively.

Input Clock

Ref1

Ref2

Time = 0.00 s

Time = 0.25 s

Time = 0.50 s

Time = 0.75 s

Time = 1.0 s

Time = 1.25 s

Time = 1.50 s

Time = 1.75 s

Output Clock

Input Clock

Ref1

Ref2

Time = 0.00 s

Time = 0.25 s

Time = 0.50 s

Time = 0.75 s

Time = 1.0 s

Time = 1.25 s

Time = 1.50 s

Time = 1.75 s

Output Clock

82V3012PVG Datasheet(PDF) 13 Page - Renesas Technology Corp

82V3012PVG Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL