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ICS93V855I Datasheet(PDF) 1 Page - Renesas Technology Corp |
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ICS93V855I Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 10 page  ICS93V855I 0783C—06/01/04 Block Diagram DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver • Low skew, low jitter PLL clock driver • External feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • With bypass mode mux • Operating frequency 60 to 170 MHz • Operating Temperature –45°C to +85°C • CYCLE - CYCLE jitter:<75ps • OUTPUT - OUTPUT skew: <60ps • Output Rise and Fall Time: 650ps - 950ps Functionality INPUTS OUTPUTS PLL State AVDD CLK_INT CLK_INC DDRT DDRC FB_OUTT FB_OUTC GND L H L H L H Bypassed/Off GND H LH LH L Bypassed/Off 2.5V (nom) LH L H L H On 2.5V (nom) HL H L H L On 2.5V (nom) <20 MHz <20 MHz Hi-Z Hi-Z Hi-Z Hi-Z Off PLL FB_INT FB_INC CLK_INC CLK_INT AVDD2.5 Control Logic FB_OUTT FB_OUTC DDRT0 DDRT1 DDRT2 DDRT3 DDRT4 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 |
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