DATASHEET

NETWORKING CLOCK SOURCE

ICS650-07C

IDT™ / ICS™ NETWORKING CLOCK SOURCE

1

ICS650-07C

REV D 102709

Description

The ICS650-07C is a low cost, low jitter, high performance

clock synthesizer for networking applications. Using analog

Phase-Locked Loop (PLL) techniques, the device accepts a

12.5 MHz or 25.00 MHz clock or fundamental mode crystal

input to produce multiple output clocks for networking chips,

PCI devices, SDRAM, and ASICs. The ICS650-07C outputs

all have 0 ppm synthesis error.

See the MK74CB214, ICS551, and ICS552-01 for non-PLL

buffer devices which produce multiple low-skew copies of

these output clocks.

See the ICS570, ICS9112-16/17/18 for zero delay buffers

that can synchronize outputs and other needed clocks.

Features

• Packaged in 20-pin tiny SSOP (QSOP)

• Pb (lead) free package

• 12.5 MHz or 25.00 MHz fundamental crystal or clock

input

• Six output clocks with selectable frequencies

• SDRAM frequencies of 67, 83, 100, and 133 MHz

• Buffered crystal reference output

• Zero ppm synthesis error in all clocks

• Ideal for PMC-Sierra’s ATM switch chips

• Full CMOS output swing with 25 mA output drive

capability at TTL levels

• Advanced, low power, sub-micron CMOS process

• 3.0 V to 5.5 V operating voltage

Block Diagram

Clock

Synthesis

and Control

Circuitry

CLKC1

CLKB1

12.5 MHz or 25.00 MHz

Crystal or Clock

CLKB2

CLKC2

OE (all outputs)

REFOUT

Clock

Buffer/

Crystal

Oscillator

X1/ICLK

X2

ACS1, 0

BCS1, 0

CCS

VDD

2

2

GND

2

2

Optional crystal capacitors are shown and

may be required for tuning of initial accuracy

CLKA1

CLKA2

/2

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